| EPSRC Reference: |
GR/H51767/01 |
| Title: |
TRANSFORMING ARCHITECTURAL MODELS INTO HIGH PERFORMANCE CONCURRENT IMPLEMENTATIONS |
| Principal Investigator: |
Furber, Professor S B |
| Other Investigators: |
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| Department: |
Computer Science |
| Organisation: |
Victoria University of Manchester, The |
| Scheme: |
Standard Research (Pre-FEC) |
| Starts: |
01 July 1992 |
Ends: |
30 June 1995 |
Value (£): |
150,467
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| EPSRC Research Topic Classifications: |
| Design & Testing Technology |
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Summary on Grant Application Form |
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The goal of this project is to develop architectural modelling and implementation tools for, and a demonstrator of, asynchronous high-performance microprocessor systems. This is being achieved by combining the high-level design tools and product and market expertise of Advanced RISC Machines Ltd. (ARM) and the high-performance VLSI process and design experience of GEC Plessey Semiconductors (GPS) with the advanced architecture and asynchronous design research skills of Manchester University. Progress:Asynchronous design techniques remove the requirement for a global clock. This allows designs to be partitioned into independent, concurrently functioning modules which operate at their own rate. Such an approach could offer a route to higher performance, greater area efficiency and lower power than that of comparable synchronous systems.The project is in its final stages, with under 6 months to run. A fully operational high-level architectural Verilog model of an asynchronous ARM processor has been implemented using a 2-phase transition signalling approach to control. The model has been used to explore different design alternatives with regard to area, power and performance.Following this, a significant design demonstrator comprising a major, self-contained section of the data path from the asynchronous ARM processor has been designed in detail. This will shortly be submitted for manufacture on GPSs new, advanced differential bipolar facility. Area considerations have necessitated the adoption of a full custom design for the data section. Control and timing are implemented as a standard cell design using elements from the GPS standard design library plus asynchronous control blocks developed by the University. The demonstrator is expected to be processed by the end of May. It will be evaluated using its automatic self-test facilities. These will not only verify the correctness of the design but also give an indication of the performance achievable by a complete microprocessor design in fast bipolar technology. The implementation of this demonstrator has required the development of new techniques, environments, architectures, processes and library elements by the University, GPS and ARM. In turn this brings the commercial exploitation of asynchronous techniques in designs closer.
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Key Findings |
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Potential use in non-academic contexts |
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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