| EP/R026084/1 | Robotics and Artificial Intelligence for Nuclear (RAIN) | (C) |
| EP/L000563/1 | Continuous on-line adaptation in many-core systems: From graceful degradation to graceful amelioration | (C) |
| EP/L000725/1 | AnyScale Applications | (C) |
| EP/K015699/1 | Interconnection Networks: Practice unites with Theory (INPUT) | (P) |
| EP/K034448/1 | PRiME: Power-efficient, Reliable, Many-core Embedded systems | (C) |
| EP/K008730/1 | PAMELA: a Panoramic Approach to the Many-CorE LAndsape - from end-user to end-device: a holistic game-changing approach | (P) |
| EP/J016330/1 | DOME: Delaying and Overcoming Microprocessor Errors | (C) |
| EP/J00457X/1 | BABEL | (P) |
| EP/I038357/1 | eFuturesXD - crossing the boundaries | (C) |
| EP/I038306/1 | Globally Asynchronous Elastic Logic Synthesis (GAELS) | (C) |
| EP/I028099/1 | Manchester Centre for Doctoral Training in Computer Science | (P) |
| EP/I016643/1 | CICADA Cross-disciplinary Feasibility Account | (C) |
| EP/G02930X/1 | VERification-Driven Asynchronous Design (VERDAD) | (P) |
| EP/G015740/1 | Biologically-Inspired Massively Parallel Architectures - computing beyond a million processors | (P) |
| EP/G013500/1 | Advanced Processor Technologies Platform Grant | (P) |
| EP/F03430X/1 | PDP-squared: Meaningful PDP language models using parallel distributed processors. | (C) |
| EP/E050441/1 | The Manchester Centre for Interdisciplinary Computational and Dynamical Analysis (CICADA) | (C) |
| EP/E001947/1 | Meeting the design challenges of the nano-CMOS electronics | (P) |
| EP/D07908X/1 | A scalable chip multiprocessor for large-scale neural simulation | (P) |
| EP/D054028/1 | Network : Developing a Common Vision for UK research in Microelectronic Design. | (C) |
| EP/C010841/1 | A Novel Computing Architecture for Cognitive Systems based on the Laminar Microcircuitry of the Neocortex | (C) |
| GR/S61270/01 | Advanced Processor Technologies Portfolio Partnership | (P) |
| GR/R73867/01 | PLATFORM GRANT - asynchronous logic systems and tools | (P) |
| GR/R91823/01 | Evaluating Test Vector Coverage Using a Layout Driven Fault Model | (P) |
| GR/S04314/01 | Visiting Fellowship for Professor Steven Nowick | (C) |
| GR/R52299/01 | VLSI Sctructures for Globally Asynchronous Systems. | (R) |
| GR/R53340/01 | VLSI Structures for Globally Asynchronous Locally Synchronous Systems | (P) |
| GR/N39159/01 | A LOW-POWER ASYNCHRONOUS DSP FOR DIGITAL MOBILE PHONE CHIPSETS | (C) |
| GR/N26432/01 | MTP: THE CENTRE FOR ADVANCED TRAINING AND EDUCATION IN COMPUTER SCIENCE | (C) |
| GR/N19618/01 | A DATAPATH COMPILER & ENHANCED SIMULATION ENVIRONMENT FOR BALSA: AN ASYNCHRONOUS SILICON SYNTHESIS SYSTEM | (C) |
| GR/M71466/01 | LOW-POWER TECHNIQUES FOR CONTACTLESS SMARTCARD APPLICATIONS | (C) |
| GR/M46396/01 | ROPA: EFFICIENT VLSI ARCHITECTURES FOR INEXACT ASSOCIATIVE MEMORIES | (P) |
| GR/M40455/01 | OPTIMISING BALSA: A SYNTHESIS SYSTEM FOR ASYNCHRONOUS CIRCUITS | (C) |
| GR/L28081/01 | UNIVERSAL PERIPHERAL CONTROLLER | (C) |
| GR/L27930/01 | LOW POWER ARCHITECTURES, CIRCUITS AND TECHNOLOGIES (POWERPACK) | (P) |
| GR/K61913/01 | DESIGN TOOLS FOR HIGH-SPEED ASYNCHRONOUS CIRCUITS | (P) |
| GR/H51767/01 | TRANSFORMING ARCHITECTURAL MODELS INTO HIGH PERFORMANCE CONCURRENT IMPLEMENTATIONS | (P) |