Details of Grant 

EPSRC Reference:	GR/R47318/01
Title:	Understanding and Utilising Fluctuations in Systems of Deep Sub-Micron MOS Devices
Principal Investigator:	Murray, Professor AF
Other Investigators:	Reekie, Dr HM
Researcher Co-Investigators:
Project Partners:	Motorola
Department:	Sch of Engineering
Organisation:	University of Edinburgh
Scheme:	Standard Research (Pre-FEC)
Starts:	01 March 2002	Ends:	30 September 2005	Value (£):	222,430
EPSRC Research Topic Classifications:	New & Emerging Comp. Paradigms System on Chip VLSI Design
EPSRC Industrial Sector Classifications:	Electronics Information Technologies
Related Grants:	GR/R47325/01
Panel History:	Panel Date Panel Name Outcome 23 May 2001 Electronics, Comms & Functional Materials Panel Deferred
Summary on Grant Application Form
Conventional computing architectures become inadequate towards the end of the Semiconductor Roadmap and straighfforward reduction in noise will ultimately be merely palliative. We will develop systematic, neural system-level approaches to reliable computation in the presence of such noise. We will investigate probabilistic architectures and circuits in this new context of Deep-Sub-Micron (DSM) devices. Detailed understanding of temporal and spatial device fluctuations will be necessary for critical evaluation of such system approaches. We will extend existing device-modelling work and use existing tools developed in Glasgow to achieve this understanding. A statistical approach to circuit simulation will be developed, whereby a representative ensemble of devices is simulated, and the results transformed into a set of compact (SPICE) models. Based on this set, a statistical ensemble of circuit simulations can be performed which span the parameter space of interest, locate regions of imperfect circuit operation, and allow design optimisation. Temporal fluctuations may be included by injection of noise of correct amplitude and spectral density at appropriate circuit nodes, using SPICE to model the influence of these fluctuations throughout the circuit. . The Product of Experts (PoE) is a computationally-efficient probabilistic architecture and we will develop models of PoE networks that incorporate, in simulation, the noise that is likely to be present in 50nm-length MOS devices.
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