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Details of Grant 

EPSRC Reference: GR/R47325/01
Title: Understanding and Utilising Fluctuations in Systems of Deep Sub-Micron MOS Devices
Principal Investigator: Roy, Professor S
Other Investigators:
Asenov, Professor A
Researcher Co-Investigators:
Project Partners:
Motorola
Department: Electronics and Electrical Engineering
Organisation: University of Glasgow
Scheme: Standard Research (Pre-FEC)
Starts: 01 October 2001 Ends: 31 March 2005 Value (£): 219,731
EPSRC Research Topic Classifications:
New & Emerging Comp. Paradigms System on Chip
VLSI Design
EPSRC Industrial Sector Classifications:
Information Technologies Electronics
Related Grants:
GR/R47318/01
Panel History:
Panel DatePanel NameOutcome
23 May 2001 Electronics, Comms & Functional Materials Panel Deferred
Summary on Grant Application Form
Convential computing architictures become inadequate towards the end of the ''Semiconductor Roadmap'' and straightforward reduction in noise will ultimatly be merely pallative. We will devolop systematic ''neural'' system-level approaces to reliable computationon the presence of such noise. We will investigate probablistic architechtures and circuits in the new context of Deep-Sub Micron DSM devices. Detailed understanding of temporal and spatial device fluctuations will be necessary for critical evaluation of such system approaches. We will extend existing device-modelling work and use existing tools devoloped in Glasgow to achieve this understanding. A statistical approach to circuit simulation will be devoloped, whereby a representative ensemble of devices is simulated, and the results transformed into a set of compact (SPICE) ,models. Based on this set, a statistical emsemble of circuit operation, and allow design optimisation. Temporal fluctulations may be included by injection of noise of correct ampitude and spectural density at appropriate circuit nodes, using SPICE to model the infulence of these fluctautions throughout the circuit. The ' Product of Experts' (PoE) is a computationally-efficent probablistic archecture and we will devope models of PoE networks that incorporate, in simulation, the noise that is likely to be present in50nm-length MOs devices.
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Organisation Website: http://www.gla.ac.uk