| EPSRC Reference: |
GR/R47325/01 |
| Title: |
Understanding and Utilising Fluctuations in Systems of Deep Sub-Micron MOS Devices |
| Principal Investigator: |
Roy, Professor S |
| Other Investigators: |
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| Researcher Co-Investigators: |
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| Project Partners: |
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| Department: |
Electronics and Electrical Engineering |
| Organisation: |
University of Glasgow |
| Scheme: |
Standard Research (Pre-FEC) |
| Starts: |
01 October 2001 |
Ends: |
31 March 2005 |
Value (£): |
219,731
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| EPSRC Research Topic Classifications: |
| New & Emerging Comp. Paradigms |
System on Chip |
| VLSI Design |
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| EPSRC Industrial Sector Classifications: |
| Electronics |
Information Technologies |
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| Related Grants: |
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| Panel History: |
| Panel Date | Panel Name | Outcome |
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23 May 2001
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Electronics, Comms & Functional Materials Panel
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Deferred
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Summary on Grant Application Form |
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Convential computing architictures become inadequate towards the end of the ''Semiconductor Roadmap'' and straightforward reduction in noise will ultimatly be merely pallative. We will devolop systematic ''neural'' system-level approaces to reliable computationon the presence of such noise. We will investigate probablistic architechtures and circuits in the new context of Deep-Sub Micron DSM devices. Detailed understanding of temporal and spatial device fluctuations will be necessary for critical evaluation of such system approaches. We will extend existing device-modelling work and use existing tools devoloped in Glasgow to achieve this understanding. A statistical approach to circuit simulation will be devoloped, whereby a representative ensemble of devices is simulated, and the results transformed into a set of compact (SPICE) ,models. Based on this set, a statistical emsemble of circuit operation, and allow design optimisation. Temporal fluctulations may be included by injection of noise of correct ampitude and spectural density at appropriate circuit nodes, using SPICE to model the infulence of these fluctautions throughout the circuit. The ' Product of Experts' (PoE) is a computationally-efficent probablistic archecture and we will devope models of PoE networks that incorporate, in simulation, the noise that is likely to be present in50nm-length MOs devices.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
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| Further Information: |
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| Organisation Website: |
http://www.gla.ac.uk |