Details of Grant 

EPSRC Reference:	GR/R16754/01
Title:	Behavioural Synthesis of Systems With Heterogeneoustiming (Besst)
Principal Investigator:	Yakovlev, Professor A
Other Investigators:	Kinniment, Professor D Koutny, Professor M Koelmans, Dr AM
Researcher Co-Investigators:
Project Partners:
Department:	Electrical, Electronic & Computer Eng
Organisation:	Newcastle University
Scheme:	Standard Research (Pre-FEC)
Starts:	01 July 2001	Ends:	30 September 2004	Value (£):	325,829
EPSRC Research Topic Classifications:	System on Chip
EPSRC Industrial Sector Classifications:	Aerospace, Defence and Marine Electronics Information Technologies
Related Grants:
Panel History:
Summary on Grant Application Form
BESST proposes to synthesise distributed, concurrent and asynchronous (DCA) kernels of systems-on-chip (SOC) from their high-level specifications. The results of this research will support the design and implementation of such systems by people with limited prior experience and at a much lower cost than it is done at present. BESST will develop a theoretical underpinning for self-timed systems synthesis, and a set of techniques and tools enabling the application of theory to designing interfaces and controllers for SOCs. These methods will be based on automatic extraction of LPNs and STGs from HDLs, and hierarchical synthesis of control circuits using a combination of direct translation and structural logic synthesis, to avoid state explosion. These methods will help to resolve the widening gap between the productivity and quality of asynchronous design automation. The new methods will generalise the existing techniques for asynchronous logic synthesis towards more generic types of DCA systems, and will extend the existing methods for synthesis of Petri nets to more pragmatic, event-based and high-level specifications and to more practically useful implementations, such as libraries of circuit components. The new tools will be integrated with Petrify; they will be tested on real life examples, such as an interface controller for a SOC, which will be fabricated using EUROCHIP facilities. The tools will be distributed within a EU-funded working group and to industrial partners, and used in training asynchronous designers.
Key Findings
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Potential use in non-academic contexts
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Impacts
Description This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk Summary Date Materialised
Sectors submitted by the Researcher
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Project URL:
Further Information:
Organisation Website:	http://www.ncl.ac.uk