| EP/N023641/1 | STRATA; Layers for Structuring Trustworthy Ambient Systems | (C) |
| EP/N031768/1 | Event-based parallel computing - partially ordered event-triggered systems (POETS) | (C) |
| EP/L025507/1 | A4A: Asynchronous design for analogue electronics | (P) |
| EP/K034448/1 | PRiME: Power-efficient, Reliable, Many-core Embedded systems | (C) |
| EP/K001698/1 | UNderstanding COmplex system eVolution through structurEd behaviouRs (UNCOVER) | (C) |
| EP/K012908/1 | Staying alive in variable, intermittent, low-power environments (SAVVIE) | (P) |
| EP/J008133/1 | Trustworthy Ambient Systems: Resource Constrained Ambience | (C) |
| EP/J005177/1 | Dream Fellowship: Energy-Modulated Computing | (P) |
| EP/I038551/1 | Globally Asynchronous Elastic Logic Synthesis (GAELS) | (P) |
| EP/I005900/1 | VARMA - Variability Modelling and Analysis Tool | (C) |
| EP/G066728/1 | Next Generation Energy-Harvesting Electronics - holistic approach 1763 | (P) |
| EP/G066361/1 | Reliable cell design methods for variable processes (RelCel) | (P) |
| EP/G037809/1 | VERification-Driven Asynchronous Design (VERDAD) | (C) |
| EP/G005273/1 | Side-channel Resistant Cryptographic IP for Smartcards | (P) |
| EP/F029012/1 | Support for the 14th International Symposium on Asynchronous Circuits and Systems (ASYNC) and 2nd International Symposium on Networks on Chip (NOCS) | (P) |
| EP/F016786/1 | Secure Design Flow | (P) |
| EP/E044662/1 | Self-Timed Event Processor | (P) |
| EP/D053064/1 | SElf-timed DATapath synthEsis (SEDATE) | (P) |
| EP/D036682/1 | Platform: Strained Si / SiGe: Materials, Technology and Design | (C) |
| EP/C512812/1 | Next Generation Of Interconnection Technology For Multiprocessor SoC | (P) |
| EP/C007298/1 | Synchronizer Reliability in the Next Generation of SoC with Multiple Clocks | (P) |
| GR/S81421/01 | Secure Circuit Design (SCREEN) | (P) |
| GR/S12036/01 | Synthesis and TEsting of Low-Latency Asynchronous circuits (STELLA) | (P) |
| GR/R32666/01 | COmputational HEteRogEneously timed NeTworks (COHERENT) | (P) |
| GR/R16754/01 | Behavioural Synthesis of Systems With Heterogeneoustiming (Besst) | (P) |
| GR/M94366/01 | MODEL VISUALISATION FOR ASYNCHRONOUS CIRCUIT DESIGN (MOVIE) | (P) |
| GR/M94359/01 | BEHAVIOURAL REFINEMENTS FOR ASYNCHRONOUS CIRCUIT SYNTHESIS (BREACH) | (P) |
| GR/L93775/01 | ASYCHRONOUS COMMUNICATION MECHANISMS FOR REAL-TIME SYSTEMS (COMFORT) | (P) |
| GR/L24038/01 | ASYNCHRONOUS CIRCUIT SYNTHESIS AND TESTING (ASTI) | (P) |
| GR/L28098/01 | TIME-PREDICTABLE HARDWARE PLATFORMS (TIMBRE) | (P) |
| GR/K70175/01 | HAZARD-FREE ARBITER DESIGN (HADES) | (P) |
| GR/J52327/01 | AUTOMATED SYNTHESIS OF SYNCHRONOUS AND ASYNCHRONOUS PARALLEL CONTROLLERS | (C) |