| EPSRC Reference: |
GR/M94359/01 |
| Title: |
BEHAVIOURAL REFINEMENTS FOR ASYNCHRONOUS CIRCUIT SYNTHESIS (BREACH) |
| Principal Investigator: |
Yakovlev, Professor A |
| Other Investigators: |
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| Department: |
Computing Sciences |
| Organisation: |
Newcastle University |
| Scheme: |
Standard Research (Pre-FEC) |
| Starts: |
27 January 2000 |
Ends: |
26 January 2002 |
Value (£): |
5,700
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| No relevance to Underpinning Sectors |
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Summary on Grant Application Form |
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1. Work towards behavioural refinement techniques in the synthesis of asynchronous control circuits will be aimed at improving current techniques for logic decomposition and technology mapping. The new methods will be based on manipulating circuit specifications at the state graph and Petri net levels, applying conditions imposed on the behavioural model by the requirements of a specific functional implementation, such as monotone (e.g. negative) gates.2. Assessment of the delay-insensitivity and speed-independence criteria for modern practical design technologies, ranging from FPGAs, PLDs to submicrom custom VLSI design, will be made, to make important conclusions about wire delays, using of explicit inverters etc. and their effect on the synthesis algorithms.3. Using the results of (1) and (3), new algorithms for logic decomposition and technology mapping tools will be developed and integrated with the existing software (e.g. Petrify).
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
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| Further Information: |
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| Organisation Website: |
http://www.ncl.ac.uk |