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Details of Grant 

EPSRC Reference: GR/M39329/01
Title: REDUCING RE-WORK COSTS FOR ASSEMBLED BOARDS
Principal Investigator: Carpenter, Dr A
Other Investigators:
Kahn, Professor H J
Researcher Co-Investigators:
Project Partners:
Pre Nexus Migration
Department: Computer Science
Organisation: Victoria University of Manchester, The
Scheme: Standard Research (Pre-FEC)
Starts: 19 April 1999 Ends: 18 April 2001 Value (£): 88,477
EPSRC Research Topic Classifications:
Design & Testing Technology
EPSRC Industrial Sector Classifications:
Manufacturing
Related Grants:
Panel History:  
Summary on Grant Application Form
This project investigated mechanisms to improve the quality and cost effectiveness of testing printed circuit assemblies (PCAs). One way that this was done was to address the fact that normally most of the information known about a PCA during its design is not passed to the manufacturing process. By using the international standard EDIF Version 4 0 0 to transfer data to the manufacturing process more semantic information could be transferred. So, for example, the manufacturing process would be aware of the components present on the PCA and of how they were interconnected rather than working only with basic geometries.Having increased the level of knowledge present in the manufacturing process, the testers present could be directly configured with the locations of components on the assembly. This avoided the traditional process of interactively configuring this data into a tester. It also meant that when a fault was detected, it was much easier to report the fault in terms of a particular component or connection not working rather the normal X-Y location on the assembly.Although knowing the particular component or interconnection that has failed is more useful than just a simple X-Y location, a re-work technician must locate this fault on a physical board in order to effect the appropriate repair. Hence, a 3D visualisation system was developed that could highlight to the technician the faulty component or interconnection. The representation of the physical board displayed by this system was obtained directly from an EDIF file.
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