| EPSRC Reference: |
GR/K97707/01 |
| Title: |
RLS FILTERING ALGORITHMS AND VLSI ARCHITECTURES FOR HIGH PERFORMANCE APPLICATIONS |
| Principal Investigator: |
Quigley, Dr SF |
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| Department: |
Electronic, Electrical and Computer Eng |
| Organisation: |
University of Birmingham |
| Scheme: |
Standard Research (Pre-FEC) |
| Starts: |
25 March 1996 |
Ends: |
01 April 1997 |
Value (£): |
81,790
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| EPSRC Research Topic Classifications: |
| Digital Signal Processing |
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Summary on Grant Application Form |
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This project aims to devise fixed point recursive Least Squares (RLS) algorithms and VLSI architectures for high performance applications such as mobile comms and radar. This will involve modifying current systolic RLS floating point algorithms to allow relatively short wordlength fixed point implementations without a reduction in the robustness, nor a significant degradation of the accuracy, of the algorithm. A number of VLSI architectures for these RLS algorithms will be generated which utilise existing work carried out in the design of high performance VLSI modules for combining square root and divide operations. Finally, a demonstrator chip for phase array radar with 16 input channels containing complex data and a sample rate of 160 Megasamples per second will be designed and implemented.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
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| Further Information: |
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| Organisation Website: |
http://www.bham.ac.uk |