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Researcher Details
 
Name: Professor RF Woods
Organisation: Queen's University of Belfast
Department: Sch of Electronics, Elec Eng & Comp Sci
Current EPSRC-Supported Research Topics:
Artificial Intelligence Electronic Devices & Subsys.
Energy Efficiency Fundamentals of Computing
Image & Vision Computing Information & Knowledge Mgmt
Instrumentation Eng. & Dev. Manufacturing Machine & Plant
Mobile Computing Networks & Distributed Systems
Structural Engineering Sustainable Energy Networks
Waste Minimisation

Current EPSRC Support
EP/Z533439/1 Digital Innovation and Circular Economy (DICE) Network+(C)
EP/Z002621/1 gran(P)
EP/Z531054/1 The Kelvin Living Lab: Towards Net Zero High-Performance Computing(C)
EP/X039218/1 eFutures: Electronic systems technology for emerging challenges(P)
EP/V02860X/1 RAPID: ReAl-time Process ModellIng and Diagnostics: Powering Digital Factories(P)
EP/W005816/1 Revolutionising Operational Safety and Economy for High-value Infrastructure using Population-based SHM (ROSEHIPS)(C)
EP/T022175/1 Kelvin-2(P)
Previous EPSRC Support
EP/X034887/1 Queen's University Belfast Core Equipment Call 2022(C)
EP/W03204X/1 NI-HPC+: Increased High Performance Computing for Data Science Applications(P)
EP/S032045/1 eFutures 2.0: Addressing Future Challenges(P)
EP/R511602/1 Impact Acceleration Account - Queen's University of Belfast 2017(P)
EP/L004232/1 ENPOWER(C)
EP/K009583/1 Programmable embedded platforms for remote and compute intensive image processing applications(P)
EP/I038357/1 eFuturesXD - crossing the boundaries(C)
EP/H051155/1 Softcore Streaming Processors for FPGA(C)
EP/F031017/1 Adaptive Hardware Systems with Novel Algorithmic Design and Guaranteed Resource Bounds(P)
EP/G000867/1 Support for International Workshop on Applied Reconfigurable Computing in 2008(P)
EP/D048605/1 SHARES - System-on-chip Heterogeneous Architecture Recognition Engine for Speech(P)
EP/D054028/1 Network : Developing a Common Vision for UK research in Microelectronic Design.(C)
EP/C000676/1 System level design methodologies based on dataflow graph models of computations(P)
GR/M66745/01 SYSTEM-ON-A-CHIP DESIGN OF AN RLS ADAPTIVE BEAMFORMER(C)
GR/L98909/01 RE-CONFIGURABLE FPGA CIRCUITS FOR CUSTOM COMPUTING APPLICATIONS(P)
GR/L27817/01 LOW POWER ARCHITECTURES, CIRCUITS AND TECHNOLOGIES (POWERPACK)(P)
GR/K97707/01 RLS FILTERING ALGORITHMS AND VLSI ARCHITECTURES FOR HIGH PERFORMANCE APPLICATIONS(C)
GR/J47729/01 ARCHITECTURAL SYNTHESIS OF VLSI SIGNAL PROCESSING CHIPS(P)
GR/G64909/01 SIGNAL PROCESSING TECHNIQUES FOR MOTION COMPENSATED TELEVISION SYSTEMS(MOTION COMPENSATION FOR TELEVISION)(C)
GR/H18791/01 CAD TOOLS FOR THE AUTOMATED DESIGN OF HIGH PERFORMANCE DSP CHIPS(C)
GR/F91254/01 THE DESIGN OF A VERY HIGH PERFORMANCE SECOND ORDER IIRFILTER CHIP(C)
GR/F39225/01 SYSTOLIC ARRAYS FOR HIGH PERFORMANCE DIGITAL SIGNAL PROCESSING(C)
Key: (P)=Principal Investigator, (C)=Co-Investigator, (R)=Researcher Co-Investigator