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Details of Grant 

EPSRC Reference: GR/J75586/01
Principal Investigator: Treleaven, Professor P
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Sira Ltd
Department: Computer Science
Organisation: UCL
Scheme: Standard Research (Pre-FEC)
Starts: 02 August 1994 Ends: 01 February 1997 Value (£): 118,082
EPSRC Research Topic Classifications:
System on Chip
EPSRC Industrial Sector Classifications:
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Summary on Grant Application Form
The objective of the project is to investigate a system architecture to offer straightforward techniques for the implementation of intelligent hardware systems, such as Neural Networks, Fuzzy Logic, Genetic Algorithms and their hybrids, at the silicon level. To this end it aims to provide a framework, through use of silicon compilation methods, that will translate a high level language definition of intelligent techniques, to a low level hardware description language. This can then be synthesised to gate level circuit descriptions and finally to integrated circuits.Progress:The development of a silicon compiler for Smart Chips consists of three major stages. The definition of a high level input language for the silicon compiler, specification of Application Specific Integrated Circuit (ASIC) hardware architectures that will be targeted by the compiler, followed by implementation of the compiler itself, plus prototyping and testing stages. Progress during the first six months of the project has been focused on the first two of these areas.The VML (Virtual Machine Language) programming language has been identified as a suitable language interface for the silicon compiler. It was developed as part of the Galatea Esprit project and is suitable for neural network definition. To test its effectiveness for use in the definition of fuzzy logic systems a number of test problems have been encoded with the language. The language currently allows limited use of fixed point number representations and is therefore being extended to allow arbitrary wordlength representation schemes. In addition certain aspects of the language are being extended to allow better definition of intelligent techniques, this includes additional logical operators for fuzzy logic and modification to the way finite wordlength multiplication is performed. It is believed that the selection of a single generic target architecture for the silicon compiler, capable of implementing all necessary functionality for any technique, will lead to inefficient ASIC design solutions. Instead a number of target architectures are being proposed suitable for different types of design problems. Three architectures have been identified as suitable for neural processing, a Generic Neuron approach using a bus based architecture, a multiplexed systolic approach and the use of distributed bit-serial methods. For fuzzy logic methods two architectures are presently under investigation, a bus based structure similar to that of the Generic Neuron and a fast feed-forward architecture. The feed-forward fuzzy processor architecture currently shows great potential in terms of speed of operation and area efficiency that should make it an attractive ASIC solution for many fuzzy system problems. The use of number representations within the hardware architecture has important ramifications on its operation and some work has been performed to assess the effects on the performance of the processor. Efficient fuzzy logic sub-structures have been developed for the fuzzification, inferencing, composition and de-fuzzification processes found in fuzzy logic systems. In addition, a paper entitled A Flexible Toolkit For Smart Chips , by Meyer Nigri, Tony Wicks and Philip Treleaven, has been accepted for the Sixth International Fuzzy Systems Association World Congress, and will be presented at the conference in July of this year.
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