| EPSRC Reference: |
GR/J64078/01 |
| Title: |
DEVELOPEMENT OF AN ANALOGUE PROCESSOR ARRAY |
| Principal Investigator: |
Hatfield, Dr J |
| Other Investigators: |
|
| Researcher Co-Investigators: |
|
| Project Partners: |
|
| Department: |
Electrical Engineering & Electronics |
| Organisation: |
UMIST |
| Scheme: |
Standard Research (Pre-FEC) |
| Starts: |
15 October 1994 |
Ends: |
14 April 1996 |
Value (£): |
50,012
|
| EPSRC Research Topic Classifications: |
| Design & Testing Technology |
|
|
| EPSRC Industrial Sector Classifications: |
|
| Related Grants: |
|
| Panel History: |
|
|
Summary on Grant Application Form |
|
The design and development of an analogue processor array, as an integrated circuit, possessing an optimum instruction set for continuous time analogue signal processing.The definition of the digitally programmable instruction set.Progress:The aim of the research is to demonstrate an analogue processor array, implemented as an integrated circuit, that can be digitally programmed in a similar manner to field programmable digital logic devices. Each cell of the array will execute mathematical functions in continuous-time on two analogue input signals. The functions to be implemented include multiplication, division, logarithm, addition, etc. The mathematical functionality is based on the logarithmic properties of the pn junction.The progress to date has seen the software SPICE simulation of a single logarithmic function implemented with the Thomson 2 micron BiCMOS process, and the subsequent submission of this log function to Thomson for fabrication as an integrated circuit through the Eurochip Initiative. Delivery of the silicon is expected in April/May 1995.The successful design and SPICE simulation of a complete analogue processor cell has also been accomplished. The cell can be digitally programmed to perform the functions of addition, negation, non-inversion, logarithm, anti-logarithm and rectification. A spare auxiliary channel is also provided. This analogue cell has now been laid-out as a full-custom cell using the Thomson 2 micron BiCMOS process, and has been submitted to RAL for fabrication through the silicon brokerage facility.
|
|
Key Findings |
|
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
|
|
Potential use in non-academic contexts |
|
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
|
|
Impacts |
|
| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
|
| Date Materialised |
|
|
|
|
Sectors submitted by the Researcher |
|
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
|
| Project URL: |
|
| Further Information: |
|
| Organisation Website: |
|