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Details of Grant 

EPSRC Reference: GR/H38133/01
Principal Investigator: Sandler, Professor M
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Department: Electronic Engineering
Organisation: Kings College London
Scheme: Standard Research (Pre-FEC)
Starts: 12 October 1992 Ends: 11 April 1996 Value (£): 87,780
EPSRC Research Topic Classifications:
Digital Signal Processing
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Summary on Grant Application Form
To investigate the new paradigm for implementation of High Order Recursive Filters (HOFs) based on the Incomplete Partial Fraction Expansion (IPFE) and related algorithms. This includes full evaluation of algorithms for filter synthesis such as already published in Proc IEE (1992) and the development of new algorithms. The investigations include examination of the performance of these filters under wordlength limitations and the construction of a hardware demonstrator.Progress:Filter design software required as a front end to define filters, has been completed. It is based on a weighted least squares technique and can design for logarithmic and linear specifications in both magnitude and frequency domains, and for a variety of error criteria. It is also possible to derive HOF specifications by high order LPC analysis and formant extraction.The IPFE algorithms generate filter structures consisting of Parallel Interconnected Subfilters (PIS). Algorithms for deriving such structures have been developed and compared, including a Generalised IPFE, based on an Undetermined Coefficients method. An important aspect is the allocation of 2nd order sections to subfilters so as to balance ranges of coefficient values in the final structure: this leads to improved dynamic performance. A package for arbitrary precision arithmetic in C has been developed and will be used in Monte Carlo simulations on the ULCC Convex computer.The main simulation software, which runs under Unix, is nearly complete. It uses Silage to specify filters so that floating point performance may be compared with fixed wordlengths. It interfaces with Simulate, an in-house simulation suite, for signal analysis, and uses Maximal Length Sequences as input stimuli, in order to obtain both linear and non-linear (ie quantization distortion) performance metrics. The system automatically optimises for signal headroom. Using this software, it has been empirically established that the main architecture under investigation (PIS) does indeed have significant advantages over conventional cascade and parallel interconnections of 2nd order sections (for high orders), thus confirming the main premise of the proposal and improving on earlier results. This has been tested up to 96th order. A simple hardware demonstrator consisting of 4 floating point DSP processors is nearly completed: any configuration of the 4 PEs is possible. Implementation of algorithms is expected over the next months. So far, there have been nine publications over the life of this grant.
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