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Details of Grant 

EPSRC Reference: GR/J88050/01
Title: A FAULT-TOLERANT ACTIVE-SUBSTRATE TECHNIQUE TO REDUCE COST AND ENSURE ON-TIME DELIVERY
Principal Investigator: Lea, Professor RM
Other Investigators:
Jalowiecki, Dr I Jalowiecki, Dr I
Researcher Co-Investigators:
Project Partners:
Brunel University London Micro Circuit Engineering
Department: Electronic & Computer Engineering
Organisation: Brunel University London
Scheme: Standard Research (Pre-FEC)
Starts: 01 September 1994 Ends: 28 February 1997 Value (£): 140,654
EPSRC Research Topic Classifications:
System on Chip VLSI Design
EPSRC Industrial Sector Classifications:
Electronics
Related Grants:
Panel History:  
Summary on Grant Application Form
Multi-Chip Modules (MCMs) offer a route to the size, weight and power dissipation constraints of embedded Massively Parallel Computers (MPCs). However, MPC manufacturers are deterred from the application of these technologies by notoriously high cost and late delivery. These problems are mainly caused by high chip counts and less than perfect chip quality, burn-in yields and mounting yields. Accordingly, this problem is often referred to as the Known-Good-Die-Problem . As a consequence, significant research effort has been directed towards the supply of Known-Good-Die . However, functional density and chip counts increase constantly and consequently, different solutions strategy has to be adopted. Brunel's involvement in the DTI-IED ITMA (Interconnection Technologies for Multi-Chip Assemblies) project has led to the recommendation of fault-tolerant active-substrate MCM as a cost-effective implementation option for Multi-Chip Modules. To that end, a demonstrator MCM will be designed, built and evaluated in real-world system. Furthermore, the acquired data will be used to improve cost models developed under ITMA and adapted under the proposed project for active-substrate MCMs.
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Organisation Website: http://www.brunel.ac.uk