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Details of Grant 

EPSRC Reference: EP/V028251/1
Title: DART: Design Accelerators by Regulating Transformations
Principal Investigator: Luk, Professor W
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Corerain Technologies Cornell University Deloitte LLP
Dunnhumby Intel Corporation Ltd Maxeler Technologies Ltd
Microsoft RIKEN Stanford University
Tianjin University University of British Columbia (UBC) Xilinx
Department: Computing
Organisation: Imperial College London
Scheme: Standard Research
Starts: 01 October 2021 Ends: 30 September 2024 Value (£): 613,910
EPSRC Research Topic Classifications:
Artificial Intelligence Electronic Devices & Subsys.
Fundamentals of Computing
EPSRC Industrial Sector Classifications:
Aerospace, Defence and Marine Information Technologies
Technical Consultancy
Related Grants:
Panel History:
Panel DatePanel NameOutcome
25 Nov 2020 Efficient Computing Peer Review Panel Announced
Summary on Grant Application Form
The DART project aims to pioneer a ground-breaking capability to enhance the performance and energy efficiency of reconfigurable hardware accelerators for next-generation computing systems. This capability will be achieved by a novel foundation for a transformation engine based on heterogeneous graphs for design optimisation and diagnosis. While hardware designers are familiar with transformations by Boolean algebra, the proposed research promotes a design-by-transformation style by providing, for the first time, tools which facilitate experimentation with design transformations and their regulation by meta-programming. These tools will cover design space exploration based on machine learning, and end-to-end tool chains mapping designs captured in multiple source languages to heterogeneous reconfigurable devices targeting cloud computing, Internet-of-Things and supercomputing. The proposed approach will be evaluated through a variety of benchmarks involving hardware acceleration, and through codifying strategies for automating the search of neural architectures for hardware implementation with both high accuracy and high efficiency.
Key Findings
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Summary
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Further Information:  
Organisation Website: http://www.imperial.ac.uk