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Name: |
Professor W Luk |
Organisation: |
Imperial College London |
Department: |
Computing |
Current EPSRC-Supported Research
Topics: |
Artificial Intelligence
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Electronic Devices & Subsys.
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Fundamentals of Computing
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Networks & Distributed Systems
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Current EPSRC Support |
EP/X036006/1 | SONNETS: Scalability Oriented Novel Network of Event Triggered Systems | (C) |
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Previous EPSRC Support |
EP/V028251/1 | DART: Design Accelerators by Regulating Transformations | (P) |
EP/S030069/1 | Centre for Spatial Computational Learning | (C) |
EP/P010040/1 | Application Customisation: Enhancing Design Quality and Developer Productivity | (P) |
EP/N031768/1 | Event-based parallel computing - partially ordered event-triggered systems (POETS) | (C) |
EP/L016796/1 | EPSRC Centre for Doctoral Training in High Performance Embedded and Distributed Systems | (P) |
EP/L00058X/1 | Exploiting Parallelism through Type Transformations for Hybrid Manycore Systems | (C) |
EP/I012036/1 | Custom Computing for Advanced Digital Systems | (P) |
EP/F033516/1 | Modular Neural Simulation with Reconfigurable Hardware | (C) |
EP/D062322/1 | Optimising Hardware Acceleration for Financial Computation | (P) |
EP/D060567/1 | Reconfigurable Architectures for Floating Point Applications | (P) |
EP/C549481/1 | PLATFORM: Field-Programmable Logic for Custom Computing | (P) |
EP/C509625/1 | Parallel Enumeration: Applications, Tools and Architectures | (P) |
GR/R55931/01 | Data Types and Elementary Functions for Custom Computing | (C) |
GR/R31409/01 | PolyNet: Policy Based Management of Adaptive Networks | (C) |
GR/N66599/01 | OPTIMISING RECONFIGURABLE HARDWARE PARALLELISM FOR CONCURRENT PROGRAMS | (P) |
GR/L59658/01 | ROPA: NON-STANDARD INTERPRETATION TECHNIQUES FOR RECONFIGURABLE HARDWARE DESIGN | (P) |
GR/L54356/01 | METHODS AND TOOLS FOR DEVELOPING RECONFIGURABLE SERIAL DESIGNS | (P) |
GR/L24366/01 | EFFECTIVE PRODUCTION OF PARAMETRISED FPGA LIBRARIES | (P) |
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Key: (P)=Principal Investigator, (C)=Co-Investigator, (R)=Researcher Co-Investigator
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