EPSRC logo

Details of Grant 

EPSRC Reference: EP/G04130X/1
Title: ENIAC MOdeling and DEsign of Reliable, process variation-aware Nanoelectronic devices, circuits and systems (MODERN)
Principal Investigator: Asenov, Professor A
Other Investigators:
Roy, Professor S
Researcher Co-Investigators:
Project Partners:
Department: Electronics and Electrical Engineering
Organisation: University of Glasgow
Scheme: Standard Research
Starts: 01 October 2009 Ends: 30 September 2012 Value (£): 716,387
EPSRC Research Topic Classifications:
Electronic Devices & Subsys.
EPSRC Industrial Sector Classifications:
Related Grants:
Panel History:
Panel DatePanel NameOutcome
01 Dec 2008 ICT Prioritisation Panel (December 2008) Announced
Summary on Grant Application Form
Increasing CMOS device variability has become one of the most acute problems facing the semiconductor manufacturing and design industries at, and beyond, the 45 nm technology generation. From all possible sources of variability the statistical variability introduced by the discreteness of charge and granularity of matter in transistors with features already of molecular dimensions is the most problematic of all. In conjunction with the statistical variability the negative bias temperature instability (NBTI) and/or hot carrier degradation can result in acute statistical reliability problems. It is widely recognized that both technology computer aided design (TCAD) and electronic design automation (EDA) tools lack the essential capabilities to predict and compass the increasing variability and reliability problems in the technology and circuit design process. This deficiency, and the corresponding tool development needs, were highlighted in the Strategic Research Agenda (SRA) of the European Nanotechnology Platform ENIAC and in the ENIAC Joint Undertaking Multi-Annual Strategic Plan. It was prioritized in the first 2008 ENIAC call for proposals and the corresponding 2008 ENIAC Annual Work Programme. The European semiconductor and design industry, research institutes and selected academia based research groups have reacted swiftly to the ENIAC call putting together a powerful consortium to address the SP7 priorities. The DMG at Glasgow, which is a world leader in the simulation and forecasting of statistical variability, has been invited as a key partner in the corresponding ENIAC MODERN proposal. This proposal is part of the funding package designed to support the DMG participation in ENIAC MODERN and includes funding from ENIAC, EPSRC and Scottish Enterprise. This will affirm the UK's leadership position in this field but more importantly will make available the associated knowledge, expertise and simulation tools to the vibrant UK CMOS device and design communities and will give a competitive advantage to the vibrant UK design industry. It will also train experts at the interface between technology, devices and design which are much needed in the UK chiples and fables design companies like ARM, CSR, Wofson Microelectronics and the numerous UK SMEs with chip design activities.
Key Findings
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Potential use in non-academic contexts
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Description This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Date Materialised
Sectors submitted by the Researcher
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Project URL:  
Further Information:  
Organisation Website: http://www.gla.ac.uk