| EPSRC Reference: |
EP/D062322/1 |
| Title: |
Optimising Hardware Acceleration for Financial Computation |
| Principal Investigator: |
Luk, Professor W |
| Other Investigators: |
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| Researcher Co-Investigators: |
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| Project Partners: |
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| Department: |
Computing |
| Organisation: |
Imperial College London |
| Scheme: |
Standard Research |
| Starts: |
01 October 2006 |
Ends: |
31 March 2010 |
Value (£): |
672,648
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| EPSRC Research Topic Classifications: |
| Artificial Intelligence |
VLSI Design |
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| EPSRC Industrial Sector Classifications: |
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| Related Grants: |
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| Panel History: |
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Summary on Grant Application Form |
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This proposal describes a three-year research project exploring novel methods and tools for hardware acceleration of financial computation in general, and for Monte Carlo simulation of financial models in particular. Our aim is to exploit the latest software and hardware technologies, particularly those based on advanced reconfigurable hardware such as FPGAs (Field-Programmable Gate Arrays), and to demonstrate the effectiveness of these technologies by applying them to overcome bottlenecks in current and future large-scale financial computation. The technical innovations of this project includes: (1) parameterisation, characterisation and efficient implementation of novel hardware architectures for financial computations; (2) exploitation of the latest software and hardware technologies, such as source-level transformation and advanced reconfigurable gate arrays; (3) techniques for reducing heat dissipation by extensive pipelining, (4) elements for an evolutionary approach to support hardware acceleration for financial analysis, such as adoption of commercial FPGA platforms, facilities to make the technology accessible to finance experts, comparison of standard fixed-point and floating point arithmetic, incremental compilation, and interface to grid technology; (5) elements for a disruptive approach to support hardware acceleration, such as run-time optimisation, coarse-grained devices, non-standard arithmetic, new application opportunities such as real-time risk analysis, and new platform and chip architectures; (6) static and dynamic customisations for adapting architectures to changes in environmental conditions to maintain effective operation, while meeting various constraints such as performance and power consumption; (7) prototype development frameworks for designing and deploying novel architectures supporting financial computations, by combining and specialising our libraries and tools; (8) large-scale applications, based on our experience in financial simulation, to drive the development of architectures and tools for novel computations.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
http://cc.doc.ic.ac.uk/finan.html |
| Further Information: |
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| Organisation Website: |
http://www.imperial.ac.uk |