| EPSRC Reference: |
EP/C000676/1 |
| Title: |
System level design methodologies based on dataflow graph models of computations |
| Principal Investigator: |
Woods, Professor RF |
| Other Investigators: |
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| Department: |
Sch of Electronics, Elec Eng & Comp Sci |
| Organisation: |
Queen's University of Belfast |
| Scheme: |
Standard Research (Pre-FEC) |
| Starts: |
01 October 2004 |
Ends: |
30 April 2008 |
Value (£): |
249,793
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Summary on Grant Application Form |
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Dataflow graph (DFG) representations are attractive for high-level capture of system specifications. Whilst tools are emerging to allow these descriptions to be mapped into multi-processor systems, there are fundamental problems with mapping functionality into hardware such as FPGAs. Hardware implementations features such as pipelining and I/O requirements can complicate the hardware generation process and application of DFG level transformations can result in horrendously complex implementations. This is further complicated by the existence of a huge bulk of IP cores whose use in a DFG design flow is not straightforward. This requires a fundamental shift in system level viewpoint of heterogeneous systems.The proposal presents a DFG-based design methodology that allows efficient hardware implementation in heterogeneous SoC platforms i.e. those comprising processors and FPGAs. This is done in a fundamentally different way such that system performance is optimised for processor/FPGA platforms. The aim is to apply transforms at the dataflow graph (DFG) level, allowing hardware implementation quality in terms of speed, circuit area and memory utilisation to be achieved quickly. One additional outcome will be the identification of additional IP core parameters to make cores more accessible at the system level.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
http://www.ecit.qub.ac.uk/Research/DigitalCommunications/ProgrammableSystemsandNetworks/Systemlevelmethodologiesforsignalprocessingsystemdesign/ |
| Further Information: |
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| Organisation Website: |
http://www.qub.ac.uk |