| DT/F002955/1 | Creation of non-volatile organic memory RFID tags (sleepertag) | (P) |
| DT/E010520/1 | Embedding of RFID tags into an electrically conductive track - TRACK-TRONIC | (P) |
| GR/R97092/01 | Carbon Based Electronics: A National Consortium | (R) |
| GR/R97115/01 | Carbon Based Electronics: A National Consortium | (R) |
| GR/R97085/01 | Carbon Based Electronics: A National Consortium | (R) |
| GR/R97092/01 | Carbon Based Electronics: A National Consortium | (P) |
| GR/R97030/01 | Carbon Based Electronics: A National Consortium - An Internal Photoemission Study of Polymer Interfaces | (R) |
| GR/R97023/01 | Carbon Based Electronics: A National Consortium | (R) |
| GR/N19564/01 | DEVELOPMENT AND EXPLOITATION OF A COMMERCIAL PLASMA OXIDATION SYSTEM | (P) |
| GR/M12032/01 | POLYMER TFTS FOR VLSI NEURAL AND DISPLAY CIRCUITS | (P) |
| GR/M18010/01 | LOW POWER ARCHITECTURE, CIRCUITS AND TECHNOLOGIES (POWER PACK) | (C) |
| GR/L54776/01 | A SIGE ON INSULATOR TECHNOLOGY FOR HIGH-SPEED, LOW POWER MOBILE COMMUNICATIONS APPLICATIONS | (C) |
| GR/L27879/01 | LOW POWER ARCHITECTURE, CIRCUITS AND TECHNOLOGIES (POWERPACK) | (C) |
| GR/K82871/01 | OXIDATION OF SIGE FOR DEVICE APPLICATION. | (C) |
| GR/J78211/01 | A STUDY OF CARRIER GENERATION AND FLOW IN POLYCRYSTALLINE SILICON | (P) |
| GR/J47323/01 | ELECTRON TRANSPORT IN ADVANCED SILICON STRUCTURES | (P) |
| GR/H79204/01 | PWN NEURAL NETWORK HARDWARE USING EEPROM TECHNOLOGY | (C) |
| GR/H65733/01 | DIELECTRICS FOR ADVANCED CMOS GATES | (C) |
| GR/H48361/01 | ASSESSMENT OF MATERIALS FOR ADVANCED SOI SUBSTRATES | (C) |
| GR/G21636/01 | HOT ELECTRON TRANSPORT AND TRAPPING IN ADVANCED MOS DEVICES | (C) |
| GR/F98574/01 | THIN FILM NEURAL NETWORKS | (C) |
| GR/F36682/01 | DIELECTRICS FOR ADVANCED CMOS GATES | (C) |
| GR/F42782/01 | POROUS SILICON (FIPOS)DEVELOPMENT | (C) |
| GR/F35180/01 | MATERIALS PROCESSING FOR ADVANCED SOI SUBSTRATES | (C) |
| GR/E45250/01 | FURTHER DEVELOPMENT OF PLASMA OXIDATION OF SILICON FOR VLSI APPLICATIONS | (P) |
| GR/E19565/01 | STUDY OF A SELF-ALIGNED HBT STRUCTURE AND SIMULATION OF FAST LOW POWER VLSI CIRCUITS EMPLOYING IT | (P) |