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| Name: |
Professor M Zwolinski |
| Organisation: |
University of Southampton |
| Department: |
Sch of Electronics and Computer Sci |
| Current EPSRC-Supported Research
Topics: |
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| Current EPSRC Support |
| There is no current EPSRC Support |
| Previous EPSRC Support |
| EP/H011420/1 | Variation-Aware Test for NanoScale CMOS Integrated Circuits | (C) |
| EP/F030991/1 | Synthesis and Optimisation of Designs Based on Novel Canonical Algebraic Structures | (C) |
| EP/E035965/1 | Electronics Design | (C) |
| EP/D079594/1 | A scalable chip multiprocessor for large-scale neural simulation | (C) |
| EP/E002064/1 | Meeting the design challenges of the nano-CMOS electronics | (P) |
| EP/D057663/1 | Reliable Low Power Embedded Computing Systems (ROPEUST) | (C) |
| EP/D022797/1 | Support for the 11th European Test Symposium (ETS) Conference in Southampton | (C) |
| EP/C512804/1 | Next Generation Of Interconnection Technology For Multiprocessor SoC | (C) |
| GR/S95770/01 | PLATFORM: System-on-chip design methods and tools | (C) |
| GR/S05557/01 | Low-Power Built-in-Self-Test (LOBIST) | (C) |
| GR/N31900/01 | HIGH FREQUENCY SWITCHED CURRENT WAVE ELLIPTIC FILTERS AND EQUALISERS BASED ON BRUTON TRANSFORMATIONS | (C) |
| GR/L35829/01 | NOVEL ALGORITHMS FOR ANALOGUE FAULT SIMULATION | (P) |
| GR/K70748/01 | HIGH-LEVEL BEHAVIOURAL SYNTHESIS FOR LOW-POWER ASICS | (C) |
| GR/K54120/01 | MIXED-SIGNAL FAULT MODELLING AND SIMULATION | (P) |
| GR/K32661/01 | TEST EVALUATION AND OPTIMISATION FOR ANALOGUE AND MIXED-SIGNAL ICS | (C) |
| GR/K00752/01 | ASYNCHRONOUS DEAD AREA TEST FOR SYNTHESIZED ASICS | (C) |
| GR/J84120/01 | NOVEL TEST METHODOLOGIES FOR MIXED-SIGNAL SYSTEMS | (C) |
| GR/H51804/01 | MIXED-MODE CIRCUIT SIMULATION | (C) |
| GR/G33929/01 | ASIC SUBSYSTEMS FOR SMART SENSORS | (C) |
| GR/F24061/01 | RESEARCH IN MIXED-MODE CIRCUIT/LOGIC LEVEL SIMULATION | (C) |
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Key: (P)=Principal Investigator, (C)=Co-Investigator, (R)=Researcher Co-Investigator
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