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Details of Grant 

EPSRC Reference: GR/T11531/01
Title: Optimisation of sub-100nm copper-interconnect & photoresist tracks for high-density IC fabrication metrology
Principal Investigator: Walton, Professor AJ
Other Investigators:
Snell, Dr AJ Stevenson, Professor JTM Bunting, Dr AS
Haworth, Dr L
Researcher Co-Investigators:
Project Partners:
NIST Nat Inst of Standards & Tech (US)
Department: Sch of Engineering
Organisation: University of Edinburgh
Scheme: Standard Research (Pre-FEC)
Starts: 01 January 2005 Ends: 30 June 2006 Value (£): 62,015
EPSRC Research Topic Classifications:
Electronic Devices & Subsys. VLSI Design
EPSRC Industrial Sector Classifications:
Electronics
Related Grants:
Panel History:  
Summary on Grant Application Form
This proposal brings together NIST, the Universities of Edinburgh and George Washington in an international research programme with two major objectives. The first is to underpin the research required for developing CD standards for future roadmap nodes with the second being to use the resulting structures and technology to initiate research on some of the more fundamental aspects of Cu based interconnect. The technology is based upon the ability to fabricate tracks and grooves with vertical sidewalls in single crystal silicon. The width of tracks can be determined using TEM technology by counting the atoms across the width of the track and multiplying by the atomic. With the completely rectangular crosssection there is the possibility of relating the resistance of the track to the TEM measured linewidth.
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Organisation Website: http://www.ed.ac.uk