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Details of Grant 

EPSRC Reference: GR/T03239/01
Title: A Novel Service-Based SoC Architecture Using On-Chip Networks with Smart Packets and Dynamically Reconfigurable Logic
Principal Investigator: Vanderbauwhede, Professor W
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Department: School of Computing Science
Organisation: University of Glasgow
Scheme: Advanced Fellowship (Pre-FEC)
Starts: 01 October 2004 Ends: 30 September 2009 Value (£): 270,926
EPSRC Research Topic Classifications:
System on Chip
EPSRC Industrial Sector Classifications:
Related Grants:
Panel History:
Panel DatePanel NameOutcome
19 Apr 2004 ICT Fellowships 2004 - ARF Interview Panel Deferred
18 Mar 2004 ICT Fellowships 2004 Sift Panel Deferred
Summary on Grant Application Form
The proposed research consists of three main components, the integration of which will result in an entirely novel System-on-a-Chip (SoC) concept:1. A service-based Networks-on-Chip (NoC) architectureService-based means that the chip offers services which will together complete a certain task, as opposed to completing the task 'ad hoc' . For a telecom integrated-circuit, the services could be descrambling, signal processing, translation between various protocols. With this approach, a single integrated-circuit could act as a generic protocol-to-protocol converter, because a service would be selected based on the desired protocol. A service-based NoC architecture makes optimal use of the network concept; it results in the decoupling of computation from communication, which is essential in managing the design of billion-transistor SoC's. This research will focus on a specific type of NoC that is self-routing and can be deployed on arbitrary physical topologies. This differs significantly to most current research, where routed networks are deployed on fixed, regular physical topologies.2. Smart packets and thin routersThe aim of this research is to develop a new network paradigm by migrating intelligence from the network nodes to the packets. Essentially, the packets contain a program in their header, and network organisation results from the concurrent execution of programs of different packets in the network nodes. This concept will result in completely self-organising networks that require only cheap, generic hardware that can be installed without any configuration. This smart packets approach is especially well suited for on-chip networks, as for these applications it is essential to keep the amount of real estate consumed by the network hardware to a minimum.3. Real-time reconfigurable logicThe smart packets concept requires an environment for the packet programs to be executed. This could be a conventional software environment, but this would be inefficient in terms of speed, computational resources and hardware cost. A better approach is to use the packet program to configure a part of a real-time reconfigurable electronic circuit. This component of the research will concentrate on the development of an architecture to enable packet-driven real-time reconfiguration. This is an entirely novel concept, as current real-time reconfigurable systems make no use of network-on-chip concepts. Ultimately, this technology could reduce a complex network router to a single real-time reconfigurable electronic circuit with a minimum of pre-programmed functionality.These three components will be integrated into a novel architecture for system-on-a-chip. Essentially, this will be a service-based NoC architecture, but the hardware performing the services will be created in real time by the smart packets. These packets can at the same time carry the data to be processed by the service. The service will create new packets with the processed data as payload and a new program, which can configure a new service, in the header. This type of SoC will combine flexibility, speed and area efficiency
Key Findings
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Organisation Website: http://www.gla.ac.uk