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Details of Grant 

EPSRC Reference: GR/S81421/01
Title: Secure Circuit Design (SCREEN)
Principal Investigator: Yakovlev, Professor A
Other Investigators:
Koutny, Professor M Koelmans, Dr AM Bystrov, Dr A
Kinniment, Professor D
Researcher Co-Investigators:
Project Partners:
Department: Electrical, Electronic & Computer Eng
Organisation: Newcastle University
Scheme: Standard Research (Pre-FEC)
Starts: 01 July 2004 Ends: 30 September 2007 Value (£): 526,124
EPSRC Research Topic Classifications:
System on Chip VLSI Design
EPSRC Industrial Sector Classifications:
Related Grants:
Panel History:  
Summary on Grant Application Form
The aim of this project is to develop a set of design methods and tools for enhancing the use of industrial EDA tools in the context of developing asynchronous hardware for secure systems. The enhanced design flow will, in the manner of contemporary synchronous flows, start from a hardware description language (such as VHDL or Verilog), where the functionality of a part will be described. After a sequence of steps through various tools, it will be able to produce a fabricatable form, i.e. the mask layout, of the specified circuit design. This flow will follow the traditional methodology for IC design, using mostly standard, existing industrial tools, enhanced only when needed by a small set of new tools, as described in the case for support. The key measure for success will be the ease with which an implementation with an improved (i.e. balanced) power signature can be generated for a complex digital design, minimising the need for the designer to learn asynchronous methods, because they will start from a neutral (i.e., not biased toward asynchronous implementation) initial specification. An additional measure of success will be the superiority of the demonstrator circuit(s), built using the new methods, with respect to a reference design, built with standard RTL techniques, in terms of the identified figures of merit (emitted EMI, security, area, etc. ). In this enhanced design flow, the system timing discipline will be considered along with other aspects affecting the circuit's security at the logic level, such as for example the use of value-masking codes and techniques for randomisation in the value and time domain. Therefore, depending on the requirements for the design, the new flow would not necessarily stipulate complete abandoning global clocking or any clocking for the entire system. In this way, our approach could be characterised as the best-effort synthesis of secure logic.The research will be undertaken in Newcastle University's Microelectronic Systems Design research group, in close collaboration with Atmel Smart Card ICs, a design and test facility at East Kilbride, specialising in high security microcontrollers. Atmel will provide this research project with important access to the industrial CAD flow and design examples for a case study chip, which will be aimed at demonstrating the impact of the self-timed logic design methods on security parameters of devices. On the design flow development, the researchers will interact with Universities of Cambridge, Manchester, Boston, Crete, Turin Polytechnic, and Cadence-Berkeley Research lab.
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Organisation Website: http://www.ncl.ac.uk