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Details of Grant 

EPSRC Reference: GR/S40855/01
Title: Logic Verification, Synthesis and Test in a New United Framework and Low Power Testable Designs
Principal Investigator: Pradhan, Professor D
Other Investigators:
Eder, Professor K
Researcher Co-Investigators:
Project Partners:
Broadcom Corporation Infineon Technologies
Department: Computer Science
Organisation: University of Bristol
Scheme: Standard Research (Pre-FEC)
Starts: 20 October 2003 Ends: 19 July 2007 Value (£): 214,007
EPSRC Research Topic Classifications:
System on Chip VLSI Design
EPSRC Industrial Sector Classifications:
Electronics
Related Grants:
Panel History:  
Summary on Grant Application Form
There are two major components of this proposed research. Firstly , a new unified framework has recently been co-developed by the principal investigator (and his former students), for solution of synthesis, verification and test problems. This framework is based on a concept called indirect implications, and is the only one which can be effectively used for all three problems.Traditionally hardware verification has been performed by regression testing: applying random and/or direct input stimulus to hardware, a software simulation, or emulation and comparing the outputs of the new design to a specification or previous design. The goal is to show equivalence between the two representations for the input space of interest.With Intel's announcement of a one billion transistor chip, it is all the more imperative that new synthesis techniques be developed - both at the logic and switch levels. One of the existing areas of research is design of SOCs for low power and ease of test. What we propose to develop is new design methodologies for low power testable RAMs. The original concept was patented by us for ease of test. New, on-going research reveals potential for low power applications, too.
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Organisation Website: http://www.bris.ac.uk