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Details of Grant 

EPSRC Reference: GR/R91823/01
Title: Evaluating Test Vector Coverage Using a Layout Driven Fault Model
Principal Investigator: Furber, Professor S B
Other Investigators:
Researcher Co-Investigators:
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Department: Computer Science
Organisation: Victoria University of Manchester, The
Scheme: ROPA
Starts: 16 September 2002 Ends: 31 March 2003 Value (£): 145,589
EPSRC Research Topic Classifications:
Electronic Devices & Subsys. VLSI Design
EPSRC Industrial Sector Classifications:
Electronics
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Panel History:  
Summary on Grant Application Form
In the production testing of integrated circuits, it is important to know the percentage of possible faults that are covered by the set of test vectors. This is achieved by fault modelling. However, traditional fault models are somewhat naive, chosen for reasons of analytic tractability and usually referring back to stuck-at faults at the schematic level which do not necessarily reflect the actuality. The proposed research will investigate fault models that reflect physical fabrication faults thus allowing a more accurate estimate of the test vector fault coverage to be made.
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