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Details of Grant 

EPSRC Reference: GR/R46281/01
Title: Built-In Self-Test of Analogue Circuits Using Transient Response Testing and Optimized Faults Sets
Principal Investigator: Taylor, Professor D
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Researcher Co-Investigators:
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Department: Sch of Computing and Engineering
Organisation: University of Huddersfield
Scheme: Fast Stream
Starts: 11 February 2002 Ends: 10 February 2005 Value (£): 49,369
EPSRC Research Topic Classifications:
System on Chip VLSI Design
EPSRC Industrial Sector Classifications:
Electronics
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Panel History:  
Summary on Grant Application Form
Initial work focused on employing Transient Response Testing as a pseudo-exhaustive functional test for linear analogue circuits. Recently this work is being extended to non-linear analogue circuits by considering Transient Response Testing as a structural test.This work has been very successful and has permitted an important conceptual leap. For a small number of example circuits it has been shown that if we consider Transient Response Testing as a structural test technique, for both linear and non-linear analogue circuits, the form of the test stimulus required and the response analysis required is almost trivial. An important part of this work has been the ability to reduce the fault set to a small and manageable, but representative, list that correlates well with what is seen in production test .With these reduced fault sets it has been shown that we can detect all faults by employing a transient response test and sampling the output response (voltage or current) just once or twice, then comparing the resulting sample with a known reference. Consequently, considering Transient Response Testing as a structural test for linear circuits would also seem to simplify the response analysis usually required. This, in turn, implies that BIST for is real possibility for analogue circuits and forms the basis of this investigation.
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Organisation Website: http://www.hud.ac.uk