EPSRC logo

Details of Grant 

EPSRC Reference: GR/R40005/01
Title: Low Power High Performance Microarchitecture and Compilation
Principal Investigator: O'Boyle, Professor M
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Edinburgh Portable Compilers Ltd
Department: Sch of Informatics
Organisation: University of Edinburgh
Scheme: Standard Research (Pre-FEC)
Starts: 01 April 2002 Ends: 30 September 2005 Value (£): 115,093
EPSRC Research Topic Classifications:
Energy Efficiency Parallel Computing
EPSRC Industrial Sector Classifications:
Information Technologies Electronics
Related Grants:
Panel History:  
Summary on Grant Application Form
Power consumption will shortly become one of the critical issues in embedded system and general purpose micro-processor architecture. The aim of this project is therefore to investigate new microarchitectural and compiler techniques to reduce power consumption. The performance and power consumption validation of these techniques are based on cycle-level power and performance architectural simulators. These tools will allow quantative analysis of the effectiveness of the proposed solutions with arbitrary architectural configurations and program workloads. This project will address the issue of realistic implementations, different methodologies and synergy between hardware and software to design low power computing systems.
Key Findings
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Potential use in non-academic contexts
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Impacts
Description This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Summary
Date Materialised
Sectors submitted by the Researcher
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Project URL:  
Further Information:  
Organisation Website: http://www.ed.ac.uk