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Details of Grant 

EPSRC Reference: GR/N66599/01
Title: OPTIMISING RECONFIGURABLE HARDWARE PARALLELISM FOR CONCURRENT PROGRAMS
Principal Investigator: Luk, Professor W
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Department: Computing
Organisation: Imperial College London
Scheme: Standard Research (Pre-FEC)
Starts: 01 April 2001 Ends: 31 December 2004 Value (£): 211,506
EPSRC Research Topic Classifications:
Parallel Computing
EPSRC Industrial Sector Classifications:
Communications Electronics
Information Technologies
Related Grants:
Panel History:  
Summary on Grant Application Form
The aim of this project is to develop methods and tools for optimising reconfigurable hardware implementation of concurrent programs. Such implementations can be realised efficiently using Field-Programmable Gate Arrays (FPGAs), which have been widely used in industry and academia, because they allow short design cycles, low development costs, in-situ upgrades, and hardware adaptation to run-time conditions. The proposed project combines three research strands: (1) syntax-directed compilation methods, used for concurrent languages such as Handel-C; (2) parallelisation techniques, such as pipeline vectorisation introduced by Weinhardt and Luk; (3) reconfigurable design, such as the compile-time and run-time systems by Shirazi, Luk and Cheung. The combined framework will provide a powerful means of optionally optimising parallelism and reconfiguration in implementations for concurrent programs. The project will begin with the development of methods and tools for parallelising concurrent programs; extensions to cover run-time reconfiguration and domain-specific optimisations will then be explored.
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Organisation Website: http://www.imperial.ac.uk