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Details of Grant 

EPSRC Reference: GR/N08322/01
Title: ALGORITHMS FOR LOW POWER SIGNAL PROCESSING
Principal Investigator: Arslan, Professor T
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Advanced Micro Devices Inc (AMD) Scottish Development International Wolfson Microelectronics
Department: Sch of Engineering
Organisation: University of Edinburgh
Scheme: Standard Research (Pre-FEC)
Starts: 01 June 2000 Ends: 31 May 2003 Value (£): 209,365
EPSRC Research Topic Classifications:
Digital Signal Processing VLSI Design
EPSRC Industrial Sector Classifications:
Communications Electronics
Related Grants:
Panel History:  
Summary on Grant Application Form
Power consumption is increasingly becoming a major concern in furture Silicon Technology Road Maps around the world. This is due to the significant increase in the amount of circuitry compacted into the same silicon area. This is true for both portable and high performance computing industry.Current techniques employed for power reduction are ad-how and involve significant re-design effort. This is a major overhead to an industry constrained by fast time to market and other optimisation concerns. There is an urgent demand for research into systematic methods of power reduction. This need has been elevated with the emergence of system-on-chip products where IP cores are integrated on standard bus architectures producing systems which include 8-10 Million gates! To be able to design such systems effectively and rapidly, a generic and systematic method is needed.The work proposed here aims to research into the development of a systematic method for power reduction. Power reduction will be achieved through the reduction of switched capacitance within computationally intensive components and on system buses. tHe research will target a methodology which is able to exploit parameter, data and architecture within a DSP system.
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