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Details of Grant 

EPSRC Reference: GR/M93178/01
Title: 0.03 MICRON VERTICAL SHALLOW TRENCH CMOS TECHNOLOGY
Principal Investigator: Ashburn, Professor P
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Department: Electronics and Computer Science
Organisation: University of Southampton
Scheme: Standard Research (Pre-FEC)
Starts: 01 December 2000 Ends: 31 May 2004 Value (£): 131,644
EPSRC Research Topic Classifications:
Electronic Devices & Subsys.
EPSRC Industrial Sector Classifications:
Electronics No relevance to Underpinning Sectors
Related Grants:
GR/M93741/01
Panel History:  
Summary on Grant Application Form
This project investigates a novel method of producing vertical MOSFETs with nanometer (0.03micron) channel lengths using a combination of epitaxy and shallow trench isolation. Alternative vertical MOS transistor architectures are investigated by simulation and fabrication, including single gate, double gate and gate-all-round structures incorporating the silicon on insulator concept. Processing modules relevant to the vertical transistor will be researched, specifically; realisation of a 5nm trench gate oxide technology with some regard to reliability; methods for reducing gate overlap capacitance; methods for maximising transistor current drive; methods of optimising the epitaxy and shallow trench isolation. The gate oxide work will emply advanced oxide characterisation techniques and the establishment of new techniques of value to UK and European industry.
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Organisation Website: http://www.soton.ac.uk