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EPSRC Reference: GR/M33280/01
Title: MICRO-CAVITY TECHNIQUES FOR GETTERING TRACE IMPURITIES IN ADVANCED SEMICONDUCTOR DEVICES
Principal Investigator: Haworth, Dr L
Other Investigators:
Gundlach, Mr A Stevenson, Professor JTM Reeves, Dr C
Researcher Co-Investigators:
Project Partners:
Motorola
Department: Sch of Engineering
Organisation: University of Edinburgh
Scheme: Standard Research (Pre-FEC)
Starts: 01 February 1999 Ends: 30 September 2002 Value (£): 178,716
EPSRC Research Topic Classifications:
Materials Characterisation Materials Processing
EPSRC Industrial Sector Classifications:
No relevance to Underpinning Sectors
Related Grants:
Panel History:  
Summary on Grant Application Form
The dissolution strength for impurities gettered by cavities appears to be greater than for alternative gettering techniques. In this project we will investigate the nature and formation of cavities introduced by implanting inert species and, in particular, will investigate the effect of cavity size, morphology and surface composition on dissolution strength with a view to optimising the gettering of metallic impurities. The cavities will be generated at various depths under MOS devices. Standard MOS transistors with a gate length of 1.5um and experimental devices with a gate length of 0.35um will be fabricated on wafers with and without gettering so that the characteristics may be compared. We will specify the optimum gettering process and the corresponding improvement in device operation.
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