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Details of Grant 

EPSRC Reference: GR/L81000/01
Title: DEVELOPMENT OF TEST STRUCTURES FOR CHARACTERISING IC TECHNOLOGIES
Principal Investigator: Walton, Professor AJ
Other Investigators:
Haworth, Dr L Murray, Professor AF
Researcher Co-Investigators:
Project Partners:
Domain Software Solutions Ltd Hewlett Packard National Semiconductor
Pre Nexus Migration Siemens
Department: Sch of Engineering
Organisation: University of Edinburgh
Scheme: Standard Research (Pre-FEC)
Starts: 01 June 1998 Ends: 28 February 2002 Value (£): 395,355
EPSRC Research Topic Classifications:
System on Chip
EPSRC Industrial Sector Classifications:
Electronics
Related Grants:
Panel History:  
Summary on Grant Application Form
The aim of the proposed project is to make cost effective use of state-of-the-art resources to research and develop the design and measurement of new and improved test structures together with developing better parameter extraction techniques for devices. This will include continued work on structures designed to measure both feature dimensions and the misregistration between layers in order to meet precisions of better than 5nm. It is planned that the work on misregistration will also include the development of holographic and diffraction techniques. Microelectronic test structures will be developed to fully characterise both oxide and damascene metal CMP processes building upon previous structures developed at Edinburgh. In addition to this, work will also take place to further characterise Wafer Level Reliability (WLR) structures that are designed to produce rapid feedback on the reliability of semiconductor products. This approach is becoming more important as reliability levels approach 10 FITs. Techniques will also be developed to produce SPICE parameters that reflect the true varience observed in manufacture while at the same time attempting to minimise the number of measurements. TCAD and statistical software will be used as an integral part of the above activities.
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Organisation Website: http://www.ed.ac.uk