| EPSRC Reference: |
GR/L74262/01 |
| Title: |
A UNIFORM SEMANTICS FOR VERILOG AND VHDL SUITABLE FOR BOTH SIMULATION AND FORMAL VERIFICATION |
| Principal Investigator: |
Greaves, Dr D |
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| Department: |
Computer Science and Technology |
| Organisation: |
University of Cambridge |
| Scheme: |
Standard Research (Pre-FEC) |
| Starts: |
01 October 1997 |
Ends: |
30 September 2000 |
Value (£): |
44,698
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Summary on Grant Application Form |
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Investigate some theoretical topics arising from ongoing research on the EPSRC project 'Checking Equivalence Between Synthesised Logic and Non-Synthesised Behavioural Prototypes'. The semantics of the VHDL and Verilog hardware description languages will be studied in depth with the goal of developing a set of core primitives that can be used to define the simulation cycles of both languages in a uniform framework. Existing simulation, verification and synthesis tools for Verilog developed at Cambridge will be reworked to use this core and hence made to support both Verilog and VHDL.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
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| Further Information: |
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| Organisation Website: |
http://www.cam.ac.uk |