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Details of Grant 

EPSRC Reference: GR/L53779/01
Title: SIGE FOR MOS TECHNOLOGIES
Principal Investigator: Thayne, Dr I
Other Investigators:
Researcher Co-Investigators:
Project Partners:
QinetiQ Siemens Zarlink
Department: Electronics and Electrical Engineering
Organisation: University of Glasgow
Scheme: Standard Research (Pre-FEC)
Starts: 01 June 1997 Ends: 31 May 2000 Value (£): 291,992
EPSRC Research Topic Classifications:
Electronic Devices & Subsys.
EPSRC Industrial Sector Classifications:
Electronics
Related Grants:
Panel History:  
Summary on Grant Application Form
A co-ordinated research activity involving principally five Universities (Glasgow, London (Imperial College), Newcastle, Southampton and Warwick) and Industry (GPS, DRA, Siemens & TMA) concerned with the evaluation and maximisation of the performance enhancement accessible through incorporating SiGe layers in Si MOSFET devices. An assessment of the possibility of using a pseudomorphic SiGe/Si structures to improve p-channel; device performance to match that of the n-channel devices in CMOS is an important early objective. The principal focus is on n- and p-channel devices produced on relaxed SiGe buffer layers (virtual substrates (VS) which already have been shown to be capable of yielding very high significant improvements in deep submicron CMOS performance. The challenge here will be to produce a commercially viable defect free VS technology and three growth centres will have a substantial activity in this area. Process development will be an important theme of the programme with e-beam lithography enabling deep submicron feature sizes to be accessed. There will be a strongly interactive modelling activity to optimise the vertical and lateral architecture of the devices. Important deliverables will be demonstrators showing the performance advantages of using SiGe devices in digital CMOS, basic micropower circuits and RF applications.
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Organisation Website: http://www.gla.ac.uk