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Details of Grant 

EPSRC Reference: GR/L53748/01
Title: SIGE FOR MOS TECHNOLOGIES
Principal Investigator: Cullis, Professor AG
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Pre Nexus Migration QinetiQ Siemens
Zarlink
Department: Electronic and Electrical Engineering
Organisation: University of Sheffield
Scheme: Standard Research (Pre-FEC)
Starts: 05 January 1998 Ends: 04 January 2001 Value (£): 133,651
EPSRC Research Topic Classifications:
Electronic Devices & Subsys. Materials Characterisation
EPSRC Industrial Sector Classifications:
Electronics
Related Grants:
Panel History:  
Summary on Grant Application Form
A co-ordinated research activity involving principally five Universities (Glasgow, London (Imperial College), Newcastle, Southampton and Warwick) and industry (GRP, DRA, Siemens and TMA) concerned with the evaluation and maximisation of the performance enhancements accessible through incorporating SiGe layers in Si MOSFET devices. An assessment of the possibility of using a pseudomorphic SiGe/Si structure to improve p-channel device performance to match that of the n-channel device in CMOS is an important early objective. The principal focus is upon n- and p- channel devices produced on relaxed SiGe buffer (virtual substrates (VS)) which have already been shown to be capable of yielding very significant improvements in deep submicron CMOS performance. The challenge here will be to produce a commercially viable defect-free VS technology and three growth centres will have a substantial activity in this area. Process development will be an important theme of the programme, with e-beam lithography enabling deep submicron feature sizes to be accessed. There will be a strongly interacting modelling activity to optimise the vertical and lateral architectures of the device. Important deliverables will be demonstrators showing the performance advantages of using SiGe devices in digital CMOS, basic micropower circuits and in RF applications.
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Organisation Website: http://www.shef.ac.uk