| EPSRC Reference: |
GR/L38530/01 |
| Title: |
DYNAMIC SYNTHESIS OF CORRECT HARDWARE |
| Principal Investigator: |
Melham, Professor T |
| Other Investigators: |
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| Researcher Co-Investigators: |
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| Project Partners: |
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| Department: |
School of Computing Science |
| Organisation: |
University of Glasgow |
| Scheme: |
Standard Research (Pre-FEC) |
| Starts: |
06 May 1997 |
Ends: |
05 May 1999 |
Value (£): |
163,063
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| EPSRC Research Topic Classifications: |
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| EPSRC Industrial Sector Classifications: |
| Aerospace, Defence and Marine |
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Summary on Grant Application Form |
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Investigation of partial evaluation of hardware as a technique to enable the exploitation of dynamic reconfiguration. The investigation involves: investigation of the design techniques to enable the generation of specialised circuits from generic circuits using the partial evaluation technique; formal verification of the algorithms that perform the specialisation; application of the technique to problems in (ATM) communications systems. The programme of work is based on the development of tools and techniques using a set of increasingly complex case studies: parallel multiplier, cryptology example (e.g. DES or RSA) and finally an ATM queuing component. As background the work involves the development of the system run-time and tools for instrumentation of the devices produced.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
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| Further Information: |
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| Organisation Website: |
http://www.gla.ac.uk |