| EPSRC Reference: |
GR/K57343/01 |
| Title: |
CHECKING EQUIVALENCE BETWEEN SYNTHESISED LOGIC AND NON-SYNTHESISABLE BEHAVIOURAL PROTOTYPES |
| Principal Investigator: |
Greaves, Dr D |
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| Department: |
Computer Science and Technology |
| Organisation: |
University of Cambridge |
| Scheme: |
Standard Research (Pre-FEC) |
| Starts: |
01 October 1995 |
Ends: |
31 December 1998 |
Value (£): |
141,459
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Summary on Grant Application Form |
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The results of this project will be useful to practicing circuit designers by enabling them to make greater use of behavioural implementations during circuit simulation while having confidence that the synthesised alternatives have equivalent functionality.It is planned to develop an algorithm to compute 'verification conditions' that are sufficient to ensure the equivalence of pains of specifications expressed in the Verilog hardware description language.The algorithm will be evaluated by implementing a practical tool for establishing the equivalence of behavioural and synthesisable specifications in Verilog. It is planned to investigate lint-like methods to check that designs are sensible and also that they are consistent with embedded assertions (whose scope and nature will be determined during the early parts of the project).
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
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| Further Information: |
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| Organisation Website: |
http://www.cam.ac.uk |