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EPSRC Reference: GR/K54915/01
Title: SIMULATION AND OPTIMISATION OF SIGE FETS FOR HIGH SPEED VLSI APPLICATIONS
Principal Investigator: Barker, Professor JR
Other Investigators:
Thorton, Dr T Joyce, Professor BA Thornton, Dr T
Asenov, Professor A
Researcher Co-Investigators:
Project Partners:
Department: Electronics and Electrical Engineering
Organisation: University of Glasgow
Scheme: Standard Research (Pre-FEC)
Starts: 01 February 1996 Ends: 31 July 1998 Value (£): 84,862
EPSRC Research Topic Classifications:
Electronic Devices & Subsys.
EPSRC Industrial Sector Classifications:
Related Grants:
Panel History:  
Summary on Grant Application Form
The changes to device architecture and advances in microfabrication now give credence for future ultra-small silicon FETs, a potential which is further strengthened by the rapid development of silicon:silicon germanium configured devices which have great promise for low noise, and high speed performances rivalling III-V based semiconductor devices. Since SiGe systems are compatible with silicon integrated circuit fabrication processes n-channel Si:SiGe FETs may in principle be used to remove the bottleneck associated with the analogue IC periphery. For CMOS integrated circuits the use of strained SiGe p-channel MOSFETS, with transconductances similar to that of conventional n-channel MOSFETs, may increase the speed and level of integration. The present proposal represents our first major step into the theoretical study, simulation and optimisation of SiGe FETs. The integration of the GU theoretical and modelling program with existing experimental SiGe device structures at ICSTM is a crucial part of our strategy.
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