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Details of Grant 

EPSRC Reference: GR/K41090/01
Principal Investigator: Austin, Professor J
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Department: Computer Science
Organisation: University of York
Scheme: Standard Research (Pre-FEC)
Starts: 01 August 1994 Ends: 31 July 1997 Value (£): 201,169
EPSRC Research Topic Classifications:
Information & Knowledge Mgmt
EPSRC Industrial Sector Classifications:
Aerospace, Defence and Marine
Related Grants:
Panel History:  
Summary on Grant Application Form
This research aims to investigate and develop the use of neural network based advanced associative memory methods to support rapid manipulation of knowledge bases in smart information system applications. The project aims to develop a system supporting high speed operations on inexact symbolic data using correlation matrix memory techniques developed at York. The primary class of applications to be addressed is realtime intelligent command and control. Progress:The project staff were appointed on 1st August 1994. John Kennedy and Ken Lees are the two RAs working on the project. Two Silicon Graphics workstations have been purchased. The CAD package Powerview has been purchased through ECAD to assist with the design of the hardware. Research has now commenced in several areas. Various methods of Superimposed coding have been studied in order to compare our approach with existing methods. This also indicated other techniques which may be of value to the project at a later date. A series of experiments has been performed to evaluate different methods for recovery of superimposed separators (intermediate patterns) produced by correlation matrix memory (CMM). This work has so far shown that trie algorithms may be most beneficial and further work is required in this area. Work has now reached a point where examples of partial matching using CMMs can be demonstrated. The possibility of using a prolog frontend is under investigation. Sicstus prolog includes external language support, which provides an interface interface to C language routines. This should enable the demonstration of AURAs capabilities in a broad context. The design of a dedicated FPGA matrix multiplier is at an advanced stage. The Sum and Threshold (SAT) processor has been fully simulated with standard delays and will shortly be simulated using true delays, after which the device will be blown and tested. Regular project meetings are held to discuss progress, plans, problems, etc. and these are held at least fortnightly. In addition, quarterly meetings are held with the industrial partner British Aerospace.
Key Findings
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Potential use in non-academic contexts
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Date Materialised
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Organisation Website: http://www.york.ac.uk