Details of Grant 

EPSRC Reference:	GR/K13820/01
Title:	RELIABILITY AND DESIGN RULES FOR DEEP SUBMICRON AND POWER INTEGRATED CIRCUIT INTERCONNECT TECHNOLOGY
Principal Investigator:	Jones, Dr B
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Department:	Physics
Organisation:	Lancaster University
Scheme:	Standard Research (Pre-FEC)
Starts:	18 July 1995	Ends:	17 July 1998	Value (£):	134,108
EPSRC Research Topic Classifications:	Design & Testing Technology
EPSRC Industrial Sector Classifications:
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Panel History:
Summary on Grant Application Form
Interconnect design rules valid for track widths from 0.1 micron up to 1mm will be determined from this project which sets out to understand failure mechanisms in integrated circuit metallisation. This will be achieved by direct observation using scanning electron microscopy (SEM) of metal microstructures under electrical stress at Cambridge which can be simulated precisely by a microstructural finite element model at Newcastle to give structural and electrical information. These data can be correlated with electrical measurements at Lancaster which have the power to investigate geometries which are not detectable by SEM. Interconnect design rules are developed through accelerated lifetesting at high temperature and high current density and then extrapolating these results to realistic circuit conditions. The use of simple empirical relationships, and the underlying assumption that there is a single failure mechanism is no longer valid given the range of operating conditions and the transition from fully polycrystalline towards bamboo microstructure in the line widths currently being considered for sub-micron geometries. There are six main themes: mechanisms of damage development, AC and interrupted testing, effects of passivation and intermetal dielectric, design rules for interconnects vias and contacts, new metallurgy, and electrical probing.
Key Findings
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Organisation Website:	http://www.lancs.ac.uk