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Details of Grant 

EPSRC Reference: GR/J84120/01
Principal Investigator: Wilkins, Dr B
Other Investigators:
Brown, Professor AD Kazmierski, Dr T Zwolinski, Professor M
Researcher Co-Investigators:
Project Partners:
Pre Nexus Migration Wolfson Microelectronics
Department: Electronics and Computer Science
Organisation: University of Southampton
Scheme: Standard Research (Pre-FEC)
Starts: 01 October 1994 Ends: 30 September 1997 Value (£): 109,591
EPSRC Research Topic Classifications:
Design & Testing Technology
EPSRC Industrial Sector Classifications:
Related Grants:
Panel History:  
Summary on Grant Application Form
(a) Evaluation of test methodologies for analogue circuits.(b) Determination of optimal test methods for a range of generic circuits.(c) Establishment of requirements to enable appropriate testability techniques to be used at ASIC, board, and system levels.This is a collaborative cluster project, being run in conjunction with the Universities of Hull and Huddersfield. It is based on the fact that all three Universities have, over the past few years, investigated the use of some form of supply current monitoring as a means of detecting faults in various analogue and mixed-signal circuits. All three partners have previously reported successful results from their experiments, but since they used different circuits and different fault-models it was not easy to make any direct comparisons of effectiveness or efficiency. This project was set up so that this comparison could be made.The work at Southampton has initially been a continuation of previous work, based on the measurement of rms supply currents under steady-state conditions. Earlier investigations of a simple flash A/D convertor have been extended to embrace larger and more realistic circuits, and the fault detection results continue to be encouraging. It has also emerged that some standard textbook circuits for this type of element incorporate redundancy and undetectable faults in the decoding logic. Once these are removed, the method can cover all open and short circuit faults in both analogue and digital parts. The second main area of investigation so far has been into simulation methods. Conscious as we are of the enormous amount of data that potentially needs to be handled, attempts are being made to speed up the process. Some success has been achieved, but not enough to make the overall problem tractable. The key will lie in the establishment of restricted but adequate fault-lists for the circuits under examination. Work; on this aspect is being vigorously pursued.One approach being followed is to make use of small-signal linear models of the circuit elements instead of using the full transistor models. The difficulty with this from our point of view is that the supply current would not normally appear in such a model. A novel circuit model has been developed to overcome this difficulty. A report on this approach is being prepared for publication and will be submitted shortly.
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Further Information:  
Organisation Website: http://www.soton.ac.uk