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Details of Grant 

EPSRC Reference: GR/J40676/01
Principal Investigator: Milne, Professor WI
Other Investigators:
Amaratunga, Professor G Ekkanath-Madathil, Professor S
Researcher Co-Investigators:
Project Partners:
Department: Engineering
Organisation: University of Cambridge
Scheme: Standard Research (Pre-FEC)
Starts: 01 November 1993 Ends: 31 July 1997 Value (£): 146,925
EPSRC Research Topic Classifications:
Power Electronics
EPSRC Industrial Sector Classifications:
Related Grants:
Panel History:  
Summary on Grant Application Form
The main aims are to produce high voltage integrated thin film transistor circuits (HVITFTs) using polycrystalline silicon. The work will cover development of novel high voltage TFT structures operating at up to 150V and monolithically integrate them with low voltage TFTs to form HVITFTs. Typical applications of these circuits are in spatial light modulators, avionic instruments and displays. Such applications will only require voltages up to 50V but to achieve switching speeds in the more novel polymer encapsulated liquid xtal devices voltages up to 150V will be needed. Progress: A commercial 2-D device simulation package has been used to investigate the novel polysilicon High Voltage Thin Film Transistor (HVTFT) structures outlined in our proposal. Initial results have been extremely encouraging and indicate that, as expected, a significant increase in the device breakdown voltage can be achieved by incorporating a semi-insulating layer between the gate and drain contacts[1]. Simulations have also suggested that further improvements in HVTFT performance can be obtained by using a dual-gated structure in which the gate electrodes are connected together by a layer of semi-insulating material. In view of the potential of the dual gated device we have filed two patents relating to this structure. A semi-insulating layer, suitable for incorporating in the novel HVTFT structures proposed, has been optimised. The semi-insulating layers have been deposited by the Plasma Enhanced Chemical Vapour Deposition (PECVD) technique from silane (SiH4), nitrous oxide (N2O) and helium (He) gas mixtures. The 'as-deposited' films are then furnace annealed at a maximum process temperature of 600C which is compatible with cheap glass substrates. The as-deposited and annealed films are completely amorphous. We have proposed a model for the microstructure of these Semi-Insulating Amorphous Oxygen-Doped Silicon (SIAOS) films and papers detailing this work have been accepted at three international conferences[2, 3, 4]. Based on our simulation results over 50 different HVTFT structures have been designed covering a range of device dimensions. A polysilicon device process is being developed in collaboration with Southampton University. The first process test batch is almost complete and will yield information on the ion implantation and anneal conditions required to dope the polysilicon source, drain and gate regions. This test batch will also provide information on the optimum anneal conditions for the solid recrystallisation of LPCVD a-Si films to form device quality polysilicon. It is expected that fabrication of the first device batch will follow shortly. Device designs for the second mask set are already being considered. Overall the project is proceeding on schedule. Further progress would have been possible were it not for the need to develop a polysilicon TFT process at Southampton. Any future polysilicon projects should benefit from this work. [1] E.M. Sankara Narayanan et al, Investigation of Novel High Voltage Polysilicon TFTs Int. Symp. Adv. Comp. Tech. in App. E.M. Systems, Seoul, June 1994.[2] F.J. Clough et al, Low Temperature Semi-insulating Oxygen Doped Silicon Films for Large Area Power Applications , Accepted for presentation at INFOS, Grenoble, June 1995.[3] F.J. Clough et al, PECVD Produced Oxygen Doped Silicon Films for High Voltage TFTs , Accepted for presentation at ICMCTF, San Diego, April 1995.[4] F.J. Clough et al, A Semi-insulating Layer for Novel High Voltage Polysilicon TFTs , Accepted for presentation at MRS Meeting, San Francisco, April 1995.
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