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Details of Grant 

EPSRC Reference: GR/H67317/01
Principal Investigator: Vass, Professor D
Other Investigators:
Robertson, Professor J Holwill, Dr R UNDERWOOD, Professor I
Bradford, Dr G Hossack, Dr W J Fancey, Dr N
Researcher Co-Investigators:
Project Partners:
Department: Sch of Physics and Astronomy
Organisation: University of Edinburgh
Scheme: Standard Research (Pre-FEC)
Starts: 01 August 1992 Ends: 31 October 1994 Value (£): 158,920
EPSRC Research Topic Classifications:
Optoelect. Devices & Circuits
EPSRC Industrial Sector Classifications:
Related Grants:
Panel History:  
Summary on Grant Application Form
The design and fabrication of liquid crystal-over-VLSI silicon spatial light modulators of high optical quality for use in coherent optical processing systems.The development of planarisation technology to produce optically flat surfaces on commercially processed silicon wafers for SLMs. Progress:A 256 x 256 pixel spatial light modulator has been designed, fabricated and used successfully in coherent optical processing systems. The device uses ferroelectric liquid crystal (BDHMerck SCE 13) over a 1.2 1.2-m CMOS silicon backplane. The backplane is organised as an array of static randomly addressed memory cells on a pitch of 40-m, the whole device including addressing circuitry being contained within a die of area 1.4 cm x 1.4 cm. The electrical output signal from each memory cell is fed through an XOR gate to an adjacent mirror-electrode on the flat surface of the silicon, the other input to the gate being driven by a universal clock signal. The bistable liquid crystal element between the pixel mirror and an ITO coated cover glass is driven in such a way that the time averaged voltage signal across the material is effectively zero, thereby eliminating electrochemical degradation of the ferroelectric liquid crystal material. The universal clock signal is fed to the ITO electrode as well as the XOR gate and this drive scheme permits the viewing of a valid image with 50% duty cycle and with the array set in the dark state during its non-active phase for ferroelectric liquid crystal in the chevron state, and >90% for the liquid crystal in the fully bistable configuration. Data are transferred to the addressing shift registers, operating at 24 MHz around the edges of the array, over a 32 bit wide data bus with 8 address code segments being clocked in sequence into a 256 bit row register in order to assemble the full row of data. The row of data is then clocked into the pixels under the control of a column select signal. Data can be loaded into the full 256 x 256 pixel array within 85-s and fully voltage balanced operation at image update rates of 3 KHz have been demonstrated. Planarisation technology has been developed to enhance the optical quality of silicon based SLMs. The silicon backplanes as received from the commercial foundry (AMS Ltd) have microstructures varying in height by up to 1.5-m and the flat mirrors carry spurious hillocks (up to 1-m) and small depressions (voids) over their surfaces. At Edinburgh the wafers have been covered with ECR-deposited silicon oxide to a thickness of ~ 4-m: the surface has been polished flat using chemical mechanical polishing techniques: vias have been etched through the oxide layer to make electrical contacts to the underlying circuitry and large area flat mirrors have been patterned in a layer of Al evaporated over the planarised structure. The pixel fill factor has been increased from ~ 26% to ~ 86%, the surface polished to ~10nm rms locally, and the liquid crystal alignment improved to produce better optical contrast.
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