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Details of Grant 

EPSRC Reference: GR/H51804/01
Principal Investigator: Brown, Professor AD
Other Investigators:
Kazmierski, Dr T Zwolinski, Professor M
Researcher Co-Investigators:
Project Partners:
Department: Electronics and Computer Science
Organisation: University of Southampton
Scheme: Standard Research (Pre-FEC)
Starts: 01 October 1992 Ends: 30 September 1995 Value (£): 81,750
EPSRC Research Topic Classifications:
Design & Testing Technology
EPSRC Industrial Sector Classifications:
Related Grants:
Panel History:  
Summary on Grant Application Form
The objective of the CLASS (Circuit Level Accuracy System Simulation) Project is to develop a simulation methodology and CAD tools to enable electronic product designs to be verified at system level, but including low level implementation dependent effects.Southamptons contribution is to develop methods for integrating digital and analogue system simulation, and provide techniques for CLASS-compatible analog-digital interfacing.The concept underlying time-domain simulation by CLASS (under development by our industrial partners in the project) is frequency-domain characterisation of a circuit followed by IFFT (inverse fast Fourier transform) to yield a time domain response. The work undertaken by us concerns extending the method to mixed mode circuits and to this we are investigating logic-to-analogue and analog-to-logic interfacing where the former is the more demanding task.We are modelling the logic-to-analog interface as a circuit which switches between different LTI (linear time invariant) versions consequent upon input logic transitions. Initially, the interface circuit has been restricted to the resistance-capacitance variety. A thorough investigation has been carried out using the impulse response matrix to obtain both the initial energy response and the applied excitation response, the latter by convolution. The former term is needed to carry energy across switching between LTI versions. Like for CLASS, the impulse response is derived from frequency-domain characterisation. While this method gave fast and accurate simulation results, compared to standard nonlinear circuit simulators, considerable pre-processing was necessary to evaluate the impulse response and storage requirements for the impulse response look-up tables were extensive. The reason for this was the need for both, a large frequency range, and a large number of frequency points, in order to achieve the necessary accuracy of the initial response term which is not smoothed by a convolving integration. Because of these limitations, an alternative method of simulating-the interface has latterly been investigated. The backward Euler stable march-in-time integration formula is very efficient in simulating an LTI version when the input excitation to the circuit is constant. The reason for this is that stored, pre-computed constant-valued, matrices can be used to drive the formula. Further, continuity of response across input logic transitions exists and so it is only necessary to switch matrices on such transitions. This method has been used to simulate both TTL and CMOS logic-to-analog interfaces and, further, has recently been extended to include both self and mutual inductive components. An extension of the method allowing some non-linearity of the logic drive output resistance is about to be investigated because this is the situation for a TTL output in its high state. A model of the analog-to-logic interface has also been implemented by detecting thresholds at which output analog voltages cause logic transitions. Both hysteric and non-hysteric threshold situations and embedding circuit induced changes of threshold are possible.
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Organisation Website: http://www.soton.ac.uk