| EPSRC Reference: |
GR/S41135/01 |
| Title: |
Test Resource Partitioning: A Low-Cost Test Scheme for Systems-on-Chip (TRAP) |
| Principal Investigator: |
Al-Hashimi, Professor B |
| Other Investigators: |
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| Department: |
Electronics and Computer Science |
| Organisation: |
University of Southampton |
| Scheme: |
Standard Research (Pre-FEC) |
| Starts: |
01 October 2003 |
Ends: |
31 January 2006 |
Value (£): |
109,211
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Summary on Grant Application Form |
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This project addresses the problem of increasing cost of test of systems-on-chip (SoC). The main objective of this research is to develop design for test (DFT) techniques to reduce the cost of testing complex digital systems consisting of embedded cores. Emphasis will be placed upon the employment of test Resource Partitioning (TRP), where most of the test is generated on chip, thus providing support for low cost testers.For this project we will exploit recent research at the University of Southampton that has produced novel cost-effective test techniques for SoC. The focus here will be on developing TRP techniques that lower the volume of test data stored on the tester using compression and decompression, and on reducing the test process dependency on the tester through the employment of embedded test architectures onto the chip. Real-world problems will provide evaluation platforms for the developed DFT techniques.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
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| Further Information: |
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| Organisation Website: |
http://www.soton.ac.uk |