| EPSRC Reference: |
GR/R13654/01 |
| Title: |
Optimizing Processor Architectures For Cryptographic Operations |
| Principal Investigator: |
May, Professor D |
| Other Investigators: |
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| Project Partners: |
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| Department: |
Computer Science |
| Organisation: |
University of Bristol |
| Scheme: |
ROPA |
| Starts: |
01 June 2001 |
Ends: |
31 May 2004 |
Value (£): |
167,741
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| EPSRC Research Topic Classifications: |
| Digital Signal Processing |
System on Chip |
| VLSI Design |
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Summary on Grant Application Form |
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This project will look at a number of ways of improving the security properties and performance characteristics of modern processors when performing cryptographic operations. The target processor types being not only those in high end servers, but also those in small constrained environments such as PDA's and Smart Cards. We aim to investigate novel approaches to producing improved performance, and approaches to reduce risk from physical side channel leakage which is utilised in attacks such as Differential Power Analysis, DPA.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
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| Further Information: |
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| Organisation Website: |
http://www.bris.ac.uk |