EPSRC Reference: |
GR/N39159/01 |
Title: |
A LOW-POWER ASYNCHRONOUS DSP FOR DIGITAL MOBILE PHONE CHIPSETS |
Principal Investigator: |
Brackenbury, Dr L |
Other Investigators: |
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Researcher Co-Investigators: |
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Project Partners: |
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Department: |
Computer Science |
Organisation: |
Victoria University of Manchester, The |
Scheme: |
Standard Research (Pre-FEC) |
Starts: |
01 October 2000 |
Ends: |
30 September 2003 |
Value (£): |
125,116
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EPSRC Research Topic Classifications: |
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EPSRC Industrial Sector Classifications: |
Communications |
Electronics |
No relevance to Underpinning Sectors |
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Related Grants: |
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Panel History: |
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Summary on Grant Application Form |
An architecture for a Digital Signal Processor (DSP) has been devised for use in next-generation digital mobile phones. It balances the high performance throughput and complex computations required in the future for this application with low Electr-Magnetic Interference (EMI) and the demand for power-efficient operation in order to extend the battery lifetime.A variety of techniques are being used to achieve this, including asynchronous timing, parallel functional units, compressed instructions, novel buffering and sign and magnitude number representation. The DSP is currently being designed down to schematic level and simulations so far performed confirm the effectiveness of the power saving techniques adopted while still maintaining high performance.The proposal seeks to realise this approach on silicon in order to prove the design. The fabricated device will then be connected to a host processor enabling the silicon to be characterised for current and the most advanced key GSM operations. Finally, the results obtained will be set in the context of other commercially available designs.
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Key Findings |
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Potential use in non-academic contexts |
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Impacts |
Description |
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Summary |
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Date Materialised |
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Sectors submitted by the Researcher |
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Project URL: |
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Further Information: |
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Organisation Website: |
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