EPSRC Reference: |
GR/N19588/01 |
Title: |
GROWTH STUDIES OF LATERALLY GROWN SELECTIVE LPCVD EPITAXIAL SI & SIGE LAYERS FOR LATERAL SIGE HBT TECH |
Principal Investigator: |
Bagnall, Professor D |
Other Investigators: |
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Researcher Co-Investigators: |
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Project Partners: |
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Department: |
Electronics and Computer Science |
Organisation: |
University of Southampton |
Scheme: |
Standard Research (Pre-FEC) |
Starts: |
01 October 2000 |
Ends: |
30 June 2004 |
Value (£): |
212,239
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EPSRC Research Topic Classifications: |
Electronic Devices & Subsys. |
Materials Processing |
Materials Synthesis & Growth |
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EPSRC Industrial Sector Classifications: |
Electronics |
No relevance to Underpinning Sectors |
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Related Grants: |
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Panel History: |
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Summary on Grant Application Form |
The first stage of the programme will involve growing both non selective and selective vertical Si and SiGe layers in small and large aspect ratio silicon dioxide windows to assess the dependence of layer growth rate, selectively, dopant incorporation, layer uniformity, and form factor on the ratio of oxide surface to window opening, with larger ratios approaching that which will be encountered in the lateral growth studies. The second stage will involve the development of suitable lateral growth cavities of various thicknesses and layout aspect ratio. Combinations of materials will be investigated including silicon dioxide and silicon nitride to achieve robust low stress structures. The third stage will involve lateral selective Si and SiGe epitaxial layer growth in the lateral growth cavities, using the results of vertical growth studies as a starting point. Structural material properties will be studied using SEM and TEM to compare with the vertical growths.The fourth stage will involve the fabrication of simple electronic devices, including lateral Si pn junction diodes, lateral Si npn bipolar transistors and lateral SiGe HBTs. D.C characterisation of these devices will yield information relating to cyrstalline perfection in the bulk and at cavity oxide sidewall semiconductor interfaces.
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Key Findings |
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Potential use in non-academic contexts |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
Summary |
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Date Materialised |
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Sectors submitted by the Researcher |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Project URL: |
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Further Information: |
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Organisation Website: |
http://www.soton.ac.uk |