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Details of Grant 

EPSRC Reference: GR/M18010/01
Title: LOW POWER ARCHITECTURE, CIRCUITS AND TECHNOLOGIES (POWER PACK)
Principal Investigator: Hall, Professor S
Other Investigators:
Eccleston, Professor W
Researcher Co-Investigators:
Project Partners:
Department: Electrical Engineering and Electronics
Organisation: University of Liverpool
Scheme: Standard Research (Pre-FEC)
Starts: 01 March 1998 Ends: 28 February 2001 Value (£): 229,935
EPSRC Research Topic Classifications:
Electronic Devices & Subsys.
EPSRC Industrial Sector Classifications:
Electronics
Related Grants:
Panel History:  
Summary on Grant Application Form
This work forms part of a collaborative cluster which has the aim of formulating a unified methodology for low power systems from architecture through clocking and circuit design technology. The Liverpool component involves devices, technology and associated circuits and logic families. A major aim of our contribution is to quantify the advantages for circuit performance of silicon-on-insulator (SOI)-CMOS technology, which arise from its known physical advantages, for this application. In particular, the low threshold voltage of SOI makes it ideal for use in pass gate logic (PGL); a known candidate for low power circuits. The research programme will include therefore, a comprehensive study of the use of complementary and single transistor PGL and investigate transient instabilities arising from the SOI floating body effect and the inherently low circuit capacitances, of concern to all SOI logic families. We will measure and assess power/delay performance for appropriate test circuits, perform characterisation and modelling of low power circuit cells proposed by ourselves and the collaborators and develop novel low power gates and solutions in both conventional and SOI-CMOS.
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Organisation Website: http://www.liv.ac.uk